公开(公告)号：US20100004018A1

公开(公告)日：2010-01-07

申请号：US12558914

申请日：2009-09-14

申请人： Alpaslan Demir ,  Leonid Kazakevich ,  Geetha L. Narayan

发明人： Alpaslan Demir ,  Leonid Kazakevich ,  Geetha L. Narayan

IPC分类号： H04B7/00

CPC分类号： H04W52/52 ,  H03F1/3247 ,  H03F1/3294 ,  H04W52/08 ,  H04W52/226

摘要： A method and system for adjusting the amplitude and phase characteristics of wireless communication signals generated by an analog radio transmitter, based on transmit power control (TPC) signals received by a base station (BS) and known characteristics of a power amplifier (PA) included in the transmitter. A digital pre-distortion compensation module, having real and imaginary signal paths, receives and processes real and imaginary signal components used to generate the wireless communication signal. The phase and amplitude characteristics of the wireless communication signal are controlled in response to the TPC signals, such that impaired amplitude and phase characteristics of the PA are corrected.

摘要翻译： 一种用于基于由基站（BS）接收的发射功率控制（TPC）信号和包括功率放大器（PA）的已知特性来调整由模拟无线电发射机产生的无线通信信号的幅度和相位特性的方法和系统 在发射机。 具有实信号路径和虚信号的数字预失真补偿模块接收并处理用于产生无线通信信号的实信号和虚信号分量。 响应于TPC信号来控制无线通信信号的相位和振幅特性，从而校正PA的幅度和相位特性受损。

公开(公告)号：US20090274248A1

公开(公告)日：2009-11-05

申请号：US12428626

申请日：2009-04-23

申请人： Edward L. Hepler ,  Geetha L. Narayan

发明人： Edward L. Hepler ,  Geetha L. Narayan

IPC分类号： H04L27/06 ,  G11C29/00

CPC分类号： H03M13/2775 ,  H03M13/2739 ,  H03M13/2764 ,  H03M13/2957 ,  H04L1/0071

摘要： A method and apparatus for contention free interleaving are disclosed. A single memory configured to use an address scheme wherein the most significant bits (MSBs) indicate which word in memory stores an interleaved piece of data. The least significant bits (LSBs) are used to calculate an index that identifies a specific soft-in/soft-out (SISO) decoder associated with a sub-word of the retrieved data. Using an interleaved address generator, the extrinsic data may be written into the memory in sequential order, but read out from the memory in interleaved order, effectively de-interleaving the data so it may be decoded. The generated interleaved address is used by SISO selector circuit which controls a multiplexer that routes the sub-word to its appropriate SISO decoder. The same address generator may be used to write interleaved extrinsic data from SISOs by reordering the sub-words, allowing the extrinsic data to be read in sequential order.

摘要翻译： 公开了一种无争用交错的方法和装置。 配置为使用地址方案的单个存储器，其中最高有效位（MSB）指示存储器中的哪个字存储交错数据段。 最低有效位（LSB）用于计算识别与检索的数据的子字相关联的特定软入/软输出（SISO）解码器的索引。 使用交错地址生成器，外部数据可以按顺序写入存储器，但是以交错顺序从存储器读出，有效地对数据进行解交织，以便其被解码。 生成的交错地址由SISO选择器电路使用，SISO选择器电路控制将子字路由到其适当的SISO解码器的多路复用器。 相同的地址生成器可以用于通过重新排序子字来从SISO写入交错的外在数据，从而允许按顺序读取外部数据。