Abstract:
A switch architecture that permits maintenance of switch signaling interfaces in switches for communication networks. The architecture provides a spare switch signaling interface that is enabled when a regular switch signaling interface is disabled. A switch matrix routes signaling channels from their dedicated position in a trunk to the spare switch signaling interface when the spare is enabled. A control processor updates a memory log associating the signaling channel and the trunks from which they originate with the spare switch signaling interface.