公开(公告)号：US12113609B2

公开(公告)日：2024-10-08

申请号：US17824540

申请日：2022-05-25

Applicant: Intel Corporation

Inventor： Laurent Cariou ,  Yaron Alpert ,  Bahareh Sadeghi ,  Robert Stacey

IPC: H04J11/00 ,  H04L1/00 ,  H04L1/1607 ,  H04L1/1867 ,  H04L5/00 ,  H04L27/26 ,  H04L41/0246 ,  H04L45/60 ,  H04L67/147 ,  H04L67/51 ,  H04Q11/00 ,  H04Q11/04 ,  H04W52/50 ,  H04W74/0816 ,  H04L9/40 ,  H04W74/0808 ,  H04W84/12 ,  H04W88/06 ,  H04W88/10

CPC classification number: H04J11/0053 ,  H04L1/0028 ,  H04L1/1621 ,  H04L1/1874 ,  H04L5/001 ,  H04L27/2602 ,  H04L41/0246 ,  H04L45/60 ,  H04L67/147 ,  H04L67/51 ,  H04Q11/00 ,  H04Q11/0428 ,  H04W52/50 ,  H04W74/0816 ,  H04L63/20 ,  H04W74/0808 ,  H04W84/12 ,  H04W88/06 ,  H04W88/10

Abstract: Simultaneous dual band operation (2.4 and 5 GHz) is common in APs on the market today, and tri-band devices are expected in the market soon. Link aggregation can also be applicable to multiple air interfaces in the same band (for instance 2 independent IEEE 802.1 lac/ax air interfaces at 5 GHz on 2 different 80 MHz channels). One exemplary aspect provides technology that enables significantly higher throughput and/or higher reliability for two stations (STAs) or a STA and the access point (AP) when the devices support simultaneous multi-band operation.

公开(公告)号：US09898993B2

公开(公告)日：2018-02-20

申请号：US14907553

申请日：2015-12-28

Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.

Inventor： Jingjing Wu ,  Zhi Xiong

IPC: G09G3/36 ,  G06F13/16 ,  H04Q9/14 ,  H04Q11/04 ,  H04J3/26

CPC classification number: G09G3/3696 ,  G06F13/1694 ,  G09G3/2092 ,  G09G3/36 ,  G09G2310/0243 ,  G09G2310/08 ,  G09G2370/08 ,  G09G2370/14 ,  H04J3/26 ,  H04Q9/14 ,  H04Q11/0428 ,  H04Q2213/13213

Abstract: The present disclosure provides method for controlling a message signal within a timing controller integrated circuit, the timing controller integrated circuit and a display panel. The method includes: receiving a low voltage differential signaling signal; decoding the low voltage differential signaling signal to obtain a transistor-transistor logic RGB data signal and a control signal, wherein the control signal comprises: a start signal, a horizontal synchronization and a vertical synchronization; processing the transistor-transistor logic RGB data signal to obtain an input RGB data; controlling a timing of the start signal before a timing of the input RGB data; and processing the input RGB data to obtain a mini-low voltage differential signaling data. Therefore, the technical scheme provided by the present disclosure has an advantage of the low cost.

公开(公告)号：US09461940B2

公开(公告)日：2016-10-04

申请号：US14326859

申请日：2014-07-09

Applicant: Foundry Networks, LLC

Inventor： Yuen Fai Wong

IPC: H04L12/28 ,  H04L12/931 ,  H04L12/46 ,  H04L12/743 ,  H04L12/935 ,  H04Q11/04 ,  H04L5/14 ,  H04L12/741

CPC classification number: H04L49/352 ,  H04L5/14 ,  H04L12/4645 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/30 ,  H04L49/3063 ,  H04Q11/0428

Abstract: The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures. A third FPGA, coupled to the first and second memory structures and a backplane, is operative to retrieve and dispatch packets to and from the first and second memory structures, compute appropriate destinations for packets and organize packets for transmission. The third FPGA is further operative to receive and dispatch packets to and from the backplane.

Abstract translation: 本发明提供了用于在一个或多个源设备与一个或多个目的地设备之间提供超过每秒10吉比特的数据传输速度的系统和方法。 根据一个实施例，本发明的系统包括第一和第二媒体访问控制（MAC）接口，以便于在相关联的一组物理接口上接收和传输分组。 该系统还考虑了耦合到MAC接口和相关联的第一和第二存储器结构的第一和第二现场可编程门阵列（FPGA），第一和第二FPGA被配置为执行从第一和第二MAC接口接收的分组的初始处理 并且调度分组到第一和第二MAC接口的传输以传输到一个或多个目的地设备。 第一和第二FPGA进一步操作以分派和从第一和第二存储器结构检索数据包。 耦合到第一和第二存储器结构和背板的第三FPGA可操作以从第一和第二存储器结构检索和分配分组，计算分组的适当目的地并组织用于传输的分组。 第三个FPGA进一步操作以从背板接收和分发分组。

公开(公告)号：US20160198040A1

公开(公告)日：2016-07-07

申请号：US14911521

申请日：2013-08-29

Applicant: Bizhan KARIMI-CHERKANDI ,  Farrokh Mohammadzadeh KOUCHRI ,  Schah Walli ALI

Inventor： Bizhan Karimi-Cherkandi ,  Farrokh Mohammadzadeh Kouchri ,  Schah Walli Ali

IPC: H04M3/22 ,  H04W28/02 ,  H04L12/26 ,  G10L15/26 ,  H04L5/00

CPC classification number: H04M3/2236 ,  G10L13/04 ,  G10L15/005 ,  G10L15/26 ,  G10L25/69 ,  H04L1/0017 ,  H04L1/20 ,  H04L5/006 ,  H04L43/16 ,  H04M3/2227 ,  H04M2201/18 ,  H04M2201/39 ,  H04M2201/40 ,  H04Q11/0428 ,  H04W28/0289

Abstract: The invention relates to a communication system and a method of maintaining audio communication in a congested communication channel currently bearing the transmission of speech in audio communication between a sender side and a receiver side, the communication channel having at least one signaling channel and at least one payload channel having a quality of service. During the audio communication the quality of service of the payload channel is monitored. If the quality of service of the payload channel is below a threshold the speech at the respective sender side is converted to text; and transmitted over the retained communication channel to the respective receiver side. The text may be converted back to speech at the receiver side.

Abstract translation: 本发明涉及一种在发送方和接收方之间的音频通信中目前承载语音传输的拥塞通信信道中保持音频通信的通信系统和方法，所述通信信道具有至少一个信令信道和至少一个信令信道 有效载荷信道具有服务质量。 在音频通信期间，监视有效载荷信道的服务质量。 如果有效载荷信道的服务质量低于阈值，则将相应发送机侧的语音转换为文本; 并通过保留的通信信道发送到相应的接收机侧。 文本可以在接收机侧被转换回到语音。

公开(公告)号：US09338291B2

公开(公告)日：2016-05-10

申请号：US14271568

申请日：2014-05-07

Applicant: International Business Machines Corporation

Inventor： Sheri G. Daye ,  Peeyush Jaiswal ,  Slobodan Sipcic ,  Fang Wang

IPC: H04M3/42 ,  H04W4/16 ,  H04M3/493 ,  H04M7/00

CPC classification number: H04M3/42348 ,  H04M3/42059 ,  H04M3/493 ,  H04M7/0033 ,  H04Q11/0428 ,  H04W4/16

Abstract: Inserting time zone information within an Integrated Services for Digital Network (ISDN) message header is provided. A time zone indicator corresponding to an origin of a communication is inserted into a time zone indicator field within a header of an ISDN message. The ISDN message with the inserted time zone indicator corresponding to the origin of the communication within the header is sent to another data processing system via a network.

Abstract translation: 在数字网络综合业务（ISDN）消息报头中插入时区信息。 对应于通信来源的时区指示符被插入到ISDN消息的报头内的时区指示符字段中。 具有与报头内的通信原点对应的插入时区指示符的ISDN消息经由网络发送到另一个数据处理系统。

公开(公告)号：US09042400B2

公开(公告)日：2015-05-26

申请号：US12165422

申请日：2008-06-30

Applicant: James A. Proctor, Jr.

Inventor： James A. Proctor, Jr.

IPC: H04L12/43 ,  H04Q11/04 ,  H04L5/00

CPC classification number: H04Q11/04 ,  H04B1/7075 ,  H04J13/0077 ,  H04J13/16 ,  H04L1/0007 ,  H04L1/1809 ,  H04L5/0007 ,  H04L7/06 ,  H04L25/14 ,  H04L27/2601 ,  H04Q11/0428 ,  H04Q2213/13098 ,  H04Q2213/13202 ,  H04Q2213/13204 ,  H04Q2213/13209 ,  H04Q2213/13216 ,  H04Q2213/1327 ,  H04Q2213/13298 ,  H04Q2213/13332 ,  H04Q2213/1336 ,  H04Q2213/13389 ,  H04W28/04 ,  H04W28/18 ,  H04W72/0446 ,  H04W74/004 ,  H04W74/04 ,  H04W74/0833 ,  H04W84/14

Abstract: A communications system improves performance of detecting a signal having an indication of a request to change communications states by making at least two positive identifications of the request in a given time frame. The system may further improve performance by applying a difference in power levels for a non-request state (i.e., steady state or ‘control hold’ state) versus a request state (i.e., ‘request to change’ state). In one particular application, a base station determines a request to change communications states with a reasonably high probability of detection and a reasonably low probability of false detection. The system has a reduced number of erroneous communications states, such as erroneous traffic channel allocations. The detection technique is compatible with 1xEV-DV systems and I-CDMA systems, but general enough to support systems employing various other communications protocols used in wired and wireless communications systems.

Abstract translation: 通信系统通过在给定的时间帧内进行至少两个请求的肯定标识来改善检测具有改变通信状态的请求的指示的信号的性能。 该系统可以通过对于非请求状态（即，稳态或“控制保持”状态）与请求状态（即，“改变请求”状态）的功率电平的差异来进一步提高性能。 在一个特定应用中，基站以相当高的检测概率确定改变通信状态的请求，并且具有相当低的错误检测概率。 该系统具有减少的错误通信状态的数量，例如错误的业务信道分配。 该检测技术与1xEV-DV系统和I-CDMA系统兼容，但一般足以支持采用有线和无线通信系统中使用的各种其他通信协议的系统。

公开(公告)号：US20150078211A1

公开(公告)日：2015-03-19

申请号：US14326859

申请日：2014-07-09

Applicant: Foundry Networks, LLC

Inventor： Yuen Fai Wong

IPC: H04L12/931 ,  H04L5/14 ,  H04L12/741 ,  H04L12/935

CPC classification number: H04L49/352 ,  H04L5/14 ,  H04L12/4645 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/30 ,  H04L49/3063 ,  H04Q11/0428

Abstract: The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures. A third FPGA, coupled to the first and second memory structures and a backplane, is operative to retrieve and dispatch packets to and from the first and second memory structures, compute appropriate destinations for packets and organize packets for transmission. The third FPGA is further operative to receive and dispatch packets to and from the backplane.

Abstract translation: 本发明提供了用于在一个或多个源设备与一个或多个目的地设备之间提供超过每秒10吉比特的数据传输速度的系统和方法。 根据一个实施例，本发明的系统包括第一和第二媒体访问控制（MAC）接口，以便于在相关联的一组物理接口上接收和传输分组。 该系统还考虑了耦合到MAC接口和相关联的第一和第二存储器结构的第一和第二现场可编程门阵列（FPGA），第一和第二FPGA被配置为执行从第一和第二MAC接口接收的分组的初始处理 并且调度分组到第一和第二MAC接口的传输以传输到一个或多个目的地设备。 第一和第二FPGA进一步操作以分派和从第一和第二存储器结构检索数据包。 耦合到第一和第二存储器结构和背板的第三FPGA可操作以从第一和第二存储器结构检索和分配分组，计算分组的适当目的地并组织用于传输的分组。 第三个FPGA进一步操作以从背板接收和分发分组。

公开(公告)号：US08792521B2

公开(公告)日：2014-07-29

申请号：US13243117

申请日：2011-09-23

Applicant: Ray (Ramon) Gomez ,  Len Dauphinee

Inventor： Ray (Ramon) Gomez ,  Len Dauphinee

IPC: H04B1/38 ,  H04L27/06 ,  H04W4/00 ,  H04J3/04

CPC classification number: H04L27/0002 ,  H04J1/085 ,  H04L5/08 ,  H04Q11/0428 ,  H04Q2213/13034 ,  H04Q2213/13039 ,  H04Q2213/13098 ,  H04Q2213/13196 ,  H04Q2213/13333

Abstract: Embodiments provide an area, cost, and power efficient multi-service transceiver architecture. The multi-service transceiver architecture simplifies receiver/transmitter front ends needed for a multi-service architecture, by replacing significant portions of multiple receiver and/or transmitter front ends with a single ADC and/or DAC, respectively. In embodiments, a plurality of received service contents are combined into one composite analog/RF signal and applied to an ADC. The ADC converts the composite signal into a composite multi-service digital signal. Digital techniques are then used to separate the plurality of service contents into a plurality of respective digital streams that each can be independently demodulated. Similarly, in the transmit direction, a plurality of digital streams, including a plurality of service contents, are combined into one composite digital signal. The composite digital signal is applied to a DAC to generate a composite multi-service analog/RF signal for subsequent transmission over a coaxial cable or wirelessly via an antenna.

Abstract translation: 实施例提供了面积，成本和功率效率的多业务收发器架构。 通过分别用单个ADC和/或DAC替代多个接收器和/或发射器前端的重要部分，多业务收发器架构简化了多业务架构所需的接收机/发射机前端。 在实施例中，将多个接收到的服务内容组合成一个复合模拟/ RF信号并将其应用于ADC。 ADC将复合信号转换为复合多业务数字信号。 然后使用数字技术将多个服务内容分成多个相应的数字流，每个可以独立地解调。 类似地，在发送方向上，包括多个服务内容的多个数字流被组合成一个复合数字信号。 复合数字信号被施加到DAC以产生复合多业务模拟/ RF信号，用于通过同轴电缆进行随后的传输或通过天线无线地进行传输。

公开(公告)号：US20120294303A1

公开(公告)日：2012-11-22

申请号：US13544077

申请日：2012-07-09

Applicant: Robert Wesley Bossemeyer, JR. ,  Dale Brian Halling ,  Scott Christopher Goering ,  Michael George Gorman ,  Denise Violetta Kagan ,  Jeffrey Neumann ,  Michael Steven Pickard ,  Michael Tisiker ,  Bruce Edward Stuckman

Inventor： Robert Wesley Bossemeyer, JR. ,  Dale Brian Halling ,  Scott Christopher Goering ,  Michael George Gorman ,  Denise Violetta Kagan ,  Jeffrey Neumann ,  Michael Steven Pickard ,  Michael Tisiker ,  Bruce Edward Stuckman

IPC: H04L12/66

CPC classification number: H04Q11/0428 ,  H04L12/2856 ,  H04L12/2883 ,  H04L12/2889 ,  H04L12/4608 ,  H04L12/5692 ,  H04L12/66 ,  H04L29/06 ,  H04L69/08 ,  H04M7/0069 ,  H04M7/1215 ,  H04M11/062 ,  H04Q11/04 ,  H04Q2213/13003 ,  H04Q2213/13034 ,  H04Q2213/13039 ,  H04Q2213/13076 ,  H04Q2213/13093 ,  H04Q2213/13096 ,  H04Q2213/13099 ,  H04Q2213/13175 ,  H04Q2213/13196 ,  H04Q2213/13202 ,  H04Q2213/13204 ,  H04Q2213/13209 ,  H04Q2213/1329 ,  H04Q2213/13296 ,  H04Q2213/13298 ,  H04Q2213/13299 ,  H04Q2213/1332 ,  H04Q2213/1334 ,  H04Q2213/13384 ,  H04Q2213/13389 ,  H04Q2213/13399

Abstract: A communications network is disclosed and includes a broadband communication line having a first derived voice channel and a second derived voice channel, wherein the first and second derived voice channels are established as a function of an available bandwidth associated with the broadband communication line. The communication network further includes a residential gateway in communication with the broadband communication line. The residential gateway includes a switch, a network interface device in communication with the switch, and wherein the switch is configured to select at least one of the first or second derived voice channels for voice communication over the broadband communication line as a function of the available bandwidth.

Abstract translation: 公开了一种通信网络，并且包括具有第一导出语音信道和第二导出话音信道的宽带通信线路，其中根据与宽带通信线路相关联的可用带宽来建立第一和第二导出话音信道。 通信网络还包括与宽带通信线路通信的住宅网关。 住宅网关包括交换机，与交换机通信的网络接口设备，并且其中交换机被配置为根据可用的方式选择第一或第二导出语音信道中的至少一个用于通过宽带通信线路进行语音通信 带宽。

公开(公告)号：US08259687B2

公开(公告)日：2012-09-04

申请号：US10767016

申请日：2004-01-29

Applicant: Lawrence R. Foore ,  James A. Proctor, Jr. ,  Thomas E. Gorsuch ,  Carlo Amalfitano

Inventor： Lawrence R. Foore ,  James A. Proctor, Jr. ,  Thomas E. Gorsuch ,  Carlo Amalfitano

IPC: H04B1/16 ,  H04O7/00 ,  H04B7/216

CPC classification number: H04W72/04 ,  H04J3/1682 ,  H04J13/16 ,  H04L1/0007 ,  H04L1/165 ,  H04L1/1809 ,  H04L25/14 ,  H04L47/14 ,  H04L47/283 ,  H04L47/29 ,  H04L47/30 ,  H04L47/70 ,  H04L47/762 ,  H04L47/803 ,  H04L47/824 ,  H04Q11/0428 ,  H04Q2213/13098 ,  H04Q2213/13202 ,  H04Q2213/13204 ,  H04Q2213/13209 ,  H04Q2213/13216 ,  H04Q2213/1327 ,  H04Q2213/13298 ,  H04Q2213/13332 ,  H04Q2213/1336 ,  H04Q2213/13389 ,  H04W24/00 ,  H04W28/0257 ,  H04W28/06 ,  H04W28/14 ,  H04W72/0406 ,  H04W72/0453 ,  H04W72/0486 ,  H04W72/1242 ,  H04W72/1252 ,  H04W74/00 ,  H04W76/10 ,  H04W80/00 ,  H04W84/14

Abstract: A code division multiple access (CDMA) user device configured to dynamically allocating at least at least one wireless communication channel to permit a more efficient allocation of wireless communication channels when providing high speed data service. The CDMA user device is configured to receive data traffic from at least one data buffer in a base station. The CDMA user device is dynamically allocated at least one wireless communication channel based on an urgency factor. The urgency factor indicates the urgency of traffic data to be transmitted from the at least one data buffer in the base station to the CDMA user device.

Abstract translation: 一种码分多址（CDMA）用户设备，被配置为动态地分配至少一个无线通信信道，以便在提供高速数据业务时能够更有效地分配无线通信信道。 CDMA用户设备被配置为从基站中的至少一个数据缓冲器接收数据业务。 基于紧急因素，CDMA用户设备动态分配至少一个无线通信信道。 紧急因素表示从基站中的至少一个数据缓冲器向CDMA用户设备发送的业务数据的紧急性。