公开(公告)号：US20240134648A1

公开(公告)日：2024-04-25

申请号：US18398107

申请日：2023-12-27

申请人： Adrian C. Hoban ,  Thijs Metsch ,  Francesc Guim Bernat ,  Niall McDonnell ,  Gershon Schatzberg

发明人： Adrian C. Hoban ,  Thijs Metsch ,  Francesc Guim Bernat ,  Niall McDonnell ,  Gershon Schatzberg

IPC分类号： G06F9/30 ,  G06F15/80

CPC分类号： G06F9/3017 ,  G06F15/8038

摘要： In one embodiment, an apparatus includes a plurality of processing cores, where each processing core is capable of executing at least one of a subset of an instruction set architecture (ISA). The apparatus also includes hardware circuitry to determine, during runtime, whether a thread comprising instructions of a particular ISA subset can execute on a particular processing core, and based on the determination, indicate a capability of the thread to be executed on the particular processing core in subsequent executions.