摘要:
In one embodiment, an apparatus includes a plurality of processing cores, where each processing core is capable of executing at least one of a subset of an instruction set architecture (ISA). The apparatus also includes hardware circuitry to determine, during runtime, whether a thread comprising instructions of a particular ISA subset can execute on a particular processing core, and based on the determination, indicate a capability of the thread to be executed on the particular processing core in subsequent executions.
摘要:
Systems and methods are disclosed for using High-level Data Link Control (HDLC) channel context information to simultaneously process multiple HDLC channels. Preferred embodiments of the present invention enable a single network processing engine to process multiple HDLC channels. The current state of the HDLC channel can be evaluated, stored, and restored, which means that the processing of a channel can be halted, the channel state read and stored, and the state of a different channel written to the processing engine. This allows the engine to begin processing a new channel, and then, at a later stage, restore the state of the original channel and resume processing.
摘要:
A media area network includes a storage system having at least one storage device for storing digitized information. A host bus adapter provides a link between the storage system and a host system that provides overall control of the media area network. Within the host bus adapter, a lower-level port driver monitors communications between the storage system and the host bus adapter. In the event of a communications failure, the lower-level port driver initiates switching from a failed port to an alternative port, thereby achieving fail-over recovery. Allocating the responsibility for fail-over recovery to the lower-level port driver assures timely handling of port failures, thereby reducing potential latency delays.
摘要:
The present invention provides systems and methods that synchronize modifications between electronic data and one or more associated data representations. Synchronization comprises translating modification made to the data or a representation to the representations or the data and other representations. A mapping engine is employed to facilitate modification translation, wherein the mapping engine utilizes data-representation relationships, which declaratively described the relationship between data and respective representations. Such relationships can be stored in markup language (e.g., xml) or as a memory string, for example. Modifications can be translated via a continuous technique, wherein translation occurs upon transaction commitment or via an explicit technique, wherein translation occurs upon an explicit request. The systems and methods further employ an adapter that facilitates communication between the mapping engine and the representation and a handler store that provides various handlers that facilitates communication between the mapping engine and data.
摘要:
The performing of actions on an object graph that contains multiple objects. The objects are categorized into partitions. Taking into account the partitions, a particular non-final action performed on the object graph may be undone without necessarily first undoing all of the one or more subsequent actions. Instead, if the subsequent actions involved objects of different partitions than the objects that were affected by the particular action desired to be undone, the particular action may be undone without undoing the subsequent actions.
摘要:
Technologies for a distributed hardware queue manager include a compute device having a procesor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.
摘要:
In some embodiments a memory controller receives a signal indicating a power condition of a system. In response to the received signal the memory controller controls a clock enable signal to a memory, allows only already issued memory controller signals to finish, and forces the memory into a self refresh. A transition is made such that power is only provided to the memory controller and to the memory, and no power is provided to any other components in the system. Other embodiments are described and claimed.
摘要:
The present invention provides systems and methods that synchronize modifications between electronic data and one or more associated data representations. Synchronization comprises translating modification made to the data or a representation to the representations or the data and other representations. A mapping engine is employed to facilitate modification translation, wherein the mapping engine utilizes data-representation relationships, which declaratively described the relationship between data and respective representations. Such relationships can be stored in markup language (e.g., xml) or as a memory string, for example. Modifications can be translated via a continuous technique, wherein translation occurs upon transaction commitment or via an explicit technique, wherein translation occurs upon an explicit request. The systems and methods further employ an adapter that facilitates communication between the mapping engine and the representation and a handler store that provides various handlers that facilitates communication between the mapping engine and data.
摘要:
An apparatus and method includes receiving frames from multiple channels, each frame partitioned into multiple timeslots, reading a timeslot lookup table including an entry that specifies an assignment associated with each timeslot, and storing the data associated with a particular timeslot in a memory location based on the assignment.