公开(公告)号：US5574847A

公开(公告)日：1996-11-12

申请号：US128893

申请日：1993-09-29

申请人： Glen A. Eckart ,  William Armstrong

发明人： Glen A. Eckart ,  William Armstrong

IPC分类号： G06T1/20 ,  G06F15/16

CPC分类号： G06T1/20

摘要： Front end processors in a graphics architecture execute parallel scan conversion and shading to process individually assigned primitive objects for providing update pixels. A crossbar along with groups of first-in-first-out registers (FIFOs) accommodates data flow to parallel pixel processors with associated memory capabilities (frame buffer banks) where visibility and blending operations are performed on predetermined sequences of update pixels to provide frame buffer pixels and ultimately display pixels. The pixel processors identify with sequences of pixels in the display in patterns designed to equalize processor loads for pixels located along scan lines of a raster, or distributed over an area. Update pixel data is tagged to identify FIFO groups (pixel processors) individual FIFO selection and output sequence. Temporal priority is accomplished so that primitive data is entered in the frame buffer banks (components) restored to the same order as generated at the central processor (CPU) level.

摘要翻译： 图形架构中的前端处理器执行并行扫描转换和阴影处理单独分配的原始对象以提供更新像素。 交叉开关与先进先出先出寄存器组（FIFO）一起容纳具有相关联的存储器能力（帧缓冲器组）的并行像素处理器的数据流，其中在预定的更新像素序列上执行可见性和混合操作以提供帧缓冲器 像素并最终显示像素。 像素处理器以显示中的像素序列来识别，其设计为使得沿着光栅的扫描线位于或分布在一个区域上的像素的处理器负载相等。 更新像素数据被标记为识别FIFO组（像素处理器）个别FIFO选择和输出序列。 完成时间优先级，使得原始数据被输入到以与在中央处理器（CPU）级产生的相同顺序恢复的帧缓冲器组（组件）中。

公开(公告)号：US5408606A

公开(公告)日：1995-04-18

申请号：US1441

申请日：1993-01-07

申请人： Glen A. Eckart

发明人： Glen A. Eckart

IPC分类号： G06T1/20 ,  G06F3/14

CPC分类号： G06T1/20

摘要： Front end processors in a graphics architecture execute parallel scan conversion and shading to first process individually assigned primitive objects for providing update pixels. A crossbar accommodates data rearrangement whereby parallel pixel processors with associated memory capabilities (frame buffer banks) perform visibility and blending operations on predetermined sequences of update pixels to provide display pixels. The pixel processors identify with sequences of pixels in the display in patterns designed to equalize processor loads for pixels located along scan lines or distributed over an area. Specific distribution criteria are disclosed for patterns. One form of pixel processor organization incorporates a distributed frame buffer with FIFO memory and control stacks. Display pixels are received by a multiplexer to supply a digital-analog connector with display data in raster sequence.

摘要翻译： 图形架构中的前端处理器执行并行扫描转换和阴影，以首先处理单独分配的原始对象以提供更新像素。 交叉开关容纳数据重排，由此具有相关联的存储器能力（帧缓冲器组）的并行像素处理器对预定的更新像素序列执行可见性和混合操作，以提供显示像素。 像素处理器以显示图案中的像素序列来识别，其设计用于对沿着扫描线定位或分布在一个区域上的像素的处理器负载进行均衡。 公布了具体分布标准的模式。 一种形式的像素处理器组合将分布式帧缓冲器与FIFO存储器和控制堆栈相结合。 显示像素由多路复用器接收，以光栅序列提供具有显示数据的数字 - 模拟连接器。

公开(公告)号：US4918626A

公开(公告)日：1990-04-17

申请号：US130811

申请日：1987-12-09

申请人： Gary S. Watkins ,  Glen A. Eckart ,  Russell A. Brown

发明人： Gary S. Watkins ,  Glen A. Eckart ,  Russell A. Brown

IPC分类号： G06T15/40 ,  G06T15/50

CPC分类号： G06T15/40 ,  G06T15/503

摘要： Image data is composed from primitives (polygons) to attain data for displays with the removal of hidden surfaces and smooth-appearing edges. Defined polygons are tested for priority in a determined field of vision by scan conversion to specify individual picture elements (pixels). Polygon contention for pixels is resolved by determining the edge of intersection between the planes of such polygons and testing the signs of certain values in accordance with predetermined criteria. Subpixel priority is treated for similar resolution to provide improved antialiased images.