公开(公告)号：US07533011B2

公开(公告)日：2009-05-12

申请号：US12124520

申请日：2008-05-21

申请人： Thomas Michael Armstead ,  Gregory Albert Dancker ,  Paul Emery Schardt

发明人： Thomas Michael Armstead ,  Gregory Albert Dancker ,  Paul Emery Schardt

IPC分类号： G06F17/50 ,  G06F11/00

CPC分类号： G06F17/5022

摘要： A simulation system includes glitch injection circuitry in one or more hardware design units to allow the injection of glitches or noise to evaluate the system's response to errors on signals between the hardware design units. The simulation system includes a stimulation module with a set of drivers to input simulation patterns into the design units. Some inputs to software models are driven by the outputs of software models of another design unit. The stimulation module can monitor these signals driven by the software model but it is difficult for the stimulation module to directly drive these signals. The added glitch circuitry allows injection of errors into the simulated hardware by the stimulation module on signals that are not directly driven by the stimulation module but are driven by the outputs of hardware design units.

摘要翻译： 模拟系统包括一个或多个硬件设计单元中的毛刺注入电路，以允许注入毛刺或噪声来评估系统对硬件设计单元之间信号上的错误的响应。 仿真系统包括具有一组驱动器的刺激模块，以将仿真模式输入到设计单元中。 软件模型的一些输入由另一个设计单元的软件模型的输出驱动。 刺激模块可以监视由软件模型驱动的这些信号，但是刺激模块难以直接驱动这些信号。 添加的毛刺电路允许刺激模块将模拟硬件注入到不直接由刺激模块驱动但由硬件设计单元的输出驱动的信号上。

公开(公告)号：US5922056A

公开(公告)日：1999-07-13

申请号：US811098

申请日：1997-03-03

申请人： Steven Joseph Amell ,  Bruce Richard Culbertson ,  Gregory Albert Dancker ,  William Van Durrett ,  Kevin Malachi Galloway ,  Harvey Gene Kiel ,  James Albert Pieterick ,  John Elliott Walker

发明人： Steven Joseph Amell ,  Bruce Richard Culbertson ,  Gregory Albert Dancker ,  William Van Durrett ,  Kevin Malachi Galloway ,  Harvey Gene Kiel ,  James Albert Pieterick ,  John Elliott Walker

IPC分类号： G06F13/42 ,  G06F13/10

CPC分类号： G06F13/4256

摘要： A computer system automatically senses characteristics of diverse peripheral devices connected to a common communications port, and automatically maximizes the communications speed with the devices. Coupled in daisy chain fashion to the communications port, all peripheral devices receive every signal issued from the controller port, each device responding only to signals addressed to that device or signals addressed to a universal address. The controller first receives an identifier from peripheral devices attached to the controller port. The controller then interprets the received identifiers to determine a maximum communications speed for each device. Next, the controller and the attached peripheral devices are configured to communicate at the maximum communications speed of the slowest device. This guarantees that all messages sent by the controller are compatible with all peripheral devices. Devices subsequently coupled to the communications port are considered by the controller, and the port and other devices are reconfigured as necessary to ensure the fastest possible communications speed.

摘要翻译： 计算机系统自动感测连接到公共通信端口的各种外围设备的特性，并且自动最大化与设备的通信速度。 所有外围设备以菊花链方式连接到通信端口，接收从控制器端口发出的每个信号，每个设备仅响应寻址到该设备的信号或寻址到通用地址的信号。 控制器首先从连接到控制器端口的外围设备接收标识符。 然后，控制器解释所接收的标识符以确定每个设备的最大通信速度。 接下来，控制器和附加的外围设备被配置为以最慢设备的最大通信速度进行通信。 这保证控制器发送的所有消息与所有外围设备兼容。 随后耦合到通信端口的设备被控制器考虑，并且端口和其他设备根据需要被重新配置以确保最快的通信速度。

公开(公告)号：US5875350A

公开(公告)日：1999-02-23

申请号：US843764

申请日：1997-04-21

申请人： Charles McLees Comp ,  Gregory Albert Dancker ,  William Van Durrett ,  Harvey Gene Kiel ,  William Wyche Plyler ,  John Elliott Walker

发明人： Charles McLees Comp ,  Gregory Albert Dancker ,  William Van Durrett ,  Harvey Gene Kiel ,  William Wyche Plyler ,  John Elliott Walker

IPC分类号： G06F13/14

CPC分类号： G06F13/4265

摘要： A controller and a properly equipped peripheral device of a computer system easily exchange messages having a compressed data format. Both the controller and the peripheral device are configured to communicate using a predefined basic command set employing a predefined communications format. The controller first verifies that the peripheral device supports a second predefined communications format in addition to the first predefined communications format. Compared to the first format, the second format utilizes messages with greater compression, i.e., an optimized bit stream ("OBS"). The controller next sends the peripheral device a number of commands, including a command of the basic command set accompanied by an OBS enable code. In the case of a write operation, the controller also sends the peripheral device an encoded dataset having the second predefined communications format and representing an underlying unencoded dataset. Although the basic command alone would alert the peripheral device to the transmission of uncompressed data, the presence of the OBS enable code signals a compressed dataset. The peripheral device receives the encoded dataset and, resulting from the received OBS enable code and the command of the basic command set, processes the encoded dataset to obtain the unencoded dataset. In the case of a read operation, the controller receives an encoded dataset, in the second predefined format, from the peripheral device.

摘要翻译： 计算机系统的控制器和适当配备的外围设备容易地交换具有压缩数据格式的消息。 控制器和外围设备都被配置为使用预定义的通信格式的预定义的基本命令集进行通信。 除了第一预定通信格式之外，控制器首先验证外围设备支持第二预定义的通信格式。 与第一格式相比，第二格式利用较大压缩的消息，即优化的比特流（“OBS”）。 控制器接下来向外围设备发送许多命令，包括伴随着OBS使能码的基本命令集的命令。 在写入操作的情况下，控制器还向外围设备发送具有第二预定通信格式的编码数据集并且表示底层未编码的数据集。 尽管基本命令本身将提醒外围设备传输未压缩数据，但OBS启用代码的存在可以表示压缩的数据集。 外围设备接收编码的数据集，并且由接收的OBS使能码和基本命令集的命令产生，处理编码的数据集以获得未编码的数据集。 在读取操作的情况下，控制器从外围设备接收第二预定格式的编码数据集。

公开(公告)号：US07428483B2

公开(公告)日：2008-09-23

申请号：US11154905

申请日：2005-06-16

申请人： Thomas Michael Armstead ,  Gregory Albert Dancker ,  Paul Emery Schardt

发明人： Thomas Michael Armstead ,  Gregory Albert Dancker ,  Paul Emery Schardt

IPC分类号： G06F17/50 ,  G06F11/00

CPC分类号： G06F17/5022

摘要： A simulation system includes glitch injection circuitry in one or more hardware design units to allow the injection of glitches or noise to evaluate the system's response to errors on signals between the hardware design units. The simulation system includes a stimulation module with a set of drivers to input simulation patterns into the design units. Some inputs to software models are driven by the outputs of software models of another design unit. The stimulation module can monitor these signals driven by the software model but it is difficult for the stimulation module to directly drive these signals. The added glitch circuitry allows injection of errors into the simulated hardware by the stimulation module on signals that are not directly driven by the stimulation module but are driven by the outputs of hardware design units.

摘要翻译： 模拟系统包括一个或多个硬件设计单元中的毛刺注入电路，以允许注入毛刺或噪声来评估系统对硬件设计单元之间信号上的错误的响应。 仿真系统包括具有一组驱动器的刺激模块，以将仿真模式输入到设计单元中。 软件模型的一些输入由另一个设计单元的软件模型的输出驱动。 刺激模块可以监视由软件模型驱动的这些信号，但刺激模块难以直接驱动这些信号。 添加的毛刺电路允许刺激模块将模拟硬件注入到不直接由刺激模块驱动但由硬件设计单元的输出驱动的信号上。

公开(公告)号：US20080221853A1

公开(公告)日：2008-09-11

申请号：US12124520

申请日：2008-05-21

申请人： Thomas Michael Armstead ,  Gregory Albert Dancker ,  Paul Emery Schardt

发明人： Thomas Michael Armstead ,  Gregory Albert Dancker ,  Paul Emery Schardt

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A simulation system includes glitch injection circuitry in one or more hardware design units to allow the injection of glitches or noise to evaluate the system's response to errors on signals between the hardware design units. The simulation system includes a stimulation module with a set of drivers to input simulation patterns into the design units. Some inputs to software models are driven by the outputs of software models of another design unit. The stimulation module can monitor these signals driven by the software model but it is difficult for the stimulation module to directly drive these signals. The added glitch circuitry allows injection of errors into the simulated hardware by the stimulation module on signals that are not directly driven by the stimulation module but are driven by the outputs of hardware design units.

摘要翻译： 模拟系统包括一个或多个硬件设计单元中的毛刺注入电路，以允许注入毛刺或噪声来评估系统对硬件设计单元之间信号上的错误的响应。 仿真系统包括具有一组驱动器的刺激模块，以将仿真模式输入到设计单元中。 软件模型的一些输入由另一个设计单元的软件模型的输出驱动。 刺激模块可以监视由软件模型驱动的这些信号，但刺激模块难以直接驱动这些信号。 添加的毛刺电路允许刺激模块将模拟硬件注入到不直接由刺激模块驱动但由硬件设计单元的输出驱动的信号上。