公开(公告)号：US5737761A

公开(公告)日：1998-04-07

申请号：US662851

申请日：1996-06-12

申请人： Stephen Holland ,  Gregory L. Tucker

发明人： Stephen Holland ,  Gregory L. Tucker

IPC分类号： G09G5/393 ,  G06F12/02

CPC分类号： G09G5/393

摘要： A subsystem architecture for direct memory access of random access memory (RAM) which performs block transfers of adjacent units of memory from one memory location to another. The architecture comprises a RAM array with write enable capability, serial access memory (SAM) registers, an alignment unit, and controller. An embodiment is described which performs bit-block transfers (BitBLTs) of pixel data within a graphical user interface (GUI) subsystem which utilizes Triple-ported Dynamic RAM (TPDRAM). The BitBLT is broken up into four cycles which handle the transfer of all possible combinations of units of adjacent memory utilizing the entire bandwidth of the port writing to RAM. The architecture allows operations to be pipelined.

摘要翻译： 用于随机存取存储器（RAM）的直接存储器访问的子系统架构，其执行从一个存储器位置到另一个存储器位置的相邻存储单元的块传输。 该架构包括具有写使能能力的RAM阵列，串行存取存储器（SAM）寄存器，对准单元和控制器。 描述了在利用三端口动态RAM（TPDRAM）的图形用户界面（GUI）子系统内执行像素数据的位块传输（BitBLT）的实施例。 BitBLT被分解成四个周期，其处理使用写入RAM的端口的整个带宽来传送相邻存储器的所有可能的相邻存储器单元的组合。 该架构允许操作被流水线化。

公开(公告)号：US5623624A

公开(公告)日：1997-04-22

申请号：US360865

申请日：1994-12-20

申请人： Stephen Holland ,  Gregory L. Tucker

发明人： Stephen Holland ,  Gregory L. Tucker

IPC分类号： G09G5/393 ,  G06F3/14

CPC分类号： G09G5/393

摘要： A subsystem architecture for direct memory access of random access memory (RAM) which performs block transfers of adjacent units of memory from one memory location to another. The architecture comprises a RAM array with write enable capability, serial access memory (SAM) registers, an alignment unit, and controller. An embodiment is described which performs bit-block transfers (BitBLTs) of pixel data within a graphical user interface (GUI) subsystem which utilizes Triple-ported Dynamic RAM (TPDRAM). The BitBLT is broken up into four cycles which handle the transfer of all possible combinations of units of adjacent memory utilizing the entire bandwidth of the port writing to RAM. The architecture allows operations to be pipelined.

摘要翻译： 用于随机存取存储器（RAM）的直接存储器访问的子系统架构，其执行从一个存储器位置到另一个存储器位置的相邻存储单元的块传输。 该架构包括具有写使能能力的RAM阵列，串行存取存储器（SAM）寄存器，对准单元和控制器。 描述了在利用三端口动态RAM（TPDRAM）的图形用户界面（GUI）子系统内执行像素数据的位块传输（BitBLT）的实施例。 BitBLT被分解成四个周期，其处理使用写入RAM的端口的整个带宽来传送相邻存储器的所有可能的相邻存储器单元的组合。 该架构允许操作被流水线化。