公开(公告)号：US4799239A

公开(公告)日：1989-01-17

申请号：US856777

申请日：1986-04-28

申请人： Sheldon Pearlman ,  Anatoly Fridland ,  Gunther J. Martin

发明人： Sheldon Pearlman ,  Anatoly Fridland ,  Gunther J. Martin

IPC分类号： H04L27/233 ,  H04L27/14

CPC分类号： H04L27/2335

摘要： A system and process for receiving phase-coherent FSK signals having data and clock components which includes a plurality of subsystems and a means for carrying data among the subsystems. At least two of the subsystems are able to communicate by means of a transmitter in one of them and a receiver in the other. The receiver includes a demodulator for separating the data and clock components of the encoded phase-coherent FSK signals. The clock demodulator includes a first transition detector and a 90-degree phase shift circuit which both receive the encoded signal. A second transition detector receives the output of the phase shift or phase delay circuit. An OR gate receives the output of the first and second transition detectors to produce a four times clock signal. The data component of the phase-coherent FSK signal is recovered by either of two alternate circuits. The first circuit uses a shift register which examines at least four samples of data in conjunction with a pair of exclusive OR gates, a NOR gate, and a flip-flop. An alternate data component demodulator includes a first 90-degree phase delay circuit and an inverter both receiving the encoded data and transmitting it to a first exclusive OR gate. A second 90-degree phase delay circuit receives the output of the first exclusive OR gate. A second exclusive OR gate receives the outputs of both the second phase delay circuit and the first exclusive OR gate.

摘要翻译： 一种用于接收具有包括多个子系统的数据和时钟分量的相位相干FSK信号的系统和过程，以及用于在子系统之间传送数据的装置。 至少两个子系统能够通过其中一个中的发射机和另一个中的接收机进行通信。 接收机包括用于分离编码的相位相干FSK信号的数据和时钟分量的解调器。 时钟解调器包括第一转换检测器和接收编码信号的90度相移电路。 第二转换检测器接收相移或相位延迟电路的输出。 或门接收第一和第二转换检测器的输出以产生四倍时钟信号。 相位相干FSK信号的数据分量由两个交替电路之一恢复。 第一个电路使用一个移位寄存器，它与一对异或门，或非门和触发器一起检查至少四个数据采样。 备用数据分量解调器包括第一90度相位延迟电路和逆变器，两者接收编码数据并将其发送到第一异或门。 第二90度相位延迟电路接收第一异或门的输出。 第二异或门接收第二相位延迟电路和第一异或门的输出。