公开(公告)号：US08958506B2

公开(公告)日：2015-02-17

申请号：US13776587

申请日：2013-02-25

申请人： Itron, Inc.

发明人： Danny Ray Seely

IPC分类号： H04L27/06 ,  H04L7/04

CPC分类号： H04L7/042 ,  H04L7/10 ,  H04L27/1566 ,  H04L27/16 ,  H04L27/2335 ,  H04L2027/003 ,  H04L2027/0046 ,  H04L2027/0065 ,  H04L2027/0085

摘要： A decoder for a modulation scheme is configured to operate close to the radio noise floor. A correlation value may be constantly updated, in an effort to match to a signature to a preamble of a packet. A low clamp value may act as a floor to which a calculated correlation value is set, if it is less than the low clamp value. If a correlation threshold is exceeded, then the correlation value is examined to determine it is a peak value. If the peak is found, power of the preamble is compared to a power threshold that is relative to the radio noise floor. If the power threshold is exceeded, positive correlation is detected. A channel optimizer is used to remove the frequency misalignment. This enables the use of a filter that is approximately equal to the occupied bandwidth of the incoming signal, further rejecting noise and interference.

摘要翻译： 用于调制方案的解码器被配置为在无线电本底噪声附近操作。 可以不断更新相关值，以便匹配到分组的前导码的签名。 如果低钳位值小于低钳位值，则低钳位值可以作为设置计算的相关值的地板。 如果超过相关阈值，则检查相关值以确定它是峰值。 如果找到峰值，则将前导码的功率与相对于无线电本底噪声的功率阈值进行比较。 如果超过功率阈值，则检测到正相关。 通道优化器用于消除频率偏移。 这使得能够使用近似等于输入信号的占用带宽的滤波器，进一步抑制噪声和干扰。

公开(公告)号：US20080008268A1

公开(公告)日：2008-01-10

申请号：US11483280

申请日：2006-07-07

申请人： Ut-Va Koc

发明人： Ut-Va Koc

IPC分类号： H04L27/22

CPC分类号： H04L27/2335 ,  H04L27/0014 ,  H04L27/2275

摘要： In one embodiment, a receiver of the invention has a detector coupled to a digital processor. The detector is adapted to mix the received PSK signal with a local oscillator (LO) signal having a time-varying phase offset with respect to the carrier frequency of the PSK signal to produce a digital measure of the PSK signal. The digital processor is adapted to: (i) estimate a frequency offset between the carrier frequency of the PSK signal and the LO signal; (ii) remove from an angular component of the digital measure a component corresponding to the frequency offset to generate a frequency-offset-adjusted signal; (iii) for each time slot of the PSK signal, estimate the phase of a respective PSK constellation symbol based on an angular component of the frequency-offset-adjusted signal and an angular component of a recursive function; (iv) estimate a phase differential for a PSK-symbol transition based on two consecutive phase estimates; (v) map each estimated phase differential onto a phase increment corresponding to a symbol transition in the PSK constellation; and (vi) recover a data sequence encoded in the PSK signal based on the mapping results.

摘要翻译： 在一个实施例中，本发明的接收机具有耦合到数字处理器的检测器。 检测器适于将接收到的PSK信号与相对于PSK信号的载波频率具有时变相位偏移的本地振荡器（LO）信号进行混合，以产生PSK信号的数字测量。 数字处理器适于：（i）估计PSK信号的载波频率和LO信号之间的频率偏移; （ii）从所述数字测量的角度分量中去除与所述频率偏移相对应的分量以产生经频偏调整的信号; （iii）对于PSK信号的每个时隙，基于频率偏移调整信号的角分量和递归函数的角分量来估计相应PSK星座符号的相位; （iv）基于两个连续相位估计来估计用于PSK符号转换的相位差; （v）将每个估计的相位差映射到对应于PSK星座中的符号转换的相位增量; 和（vi）基于映射结果恢复在PSK信号中编码的数据序列。

公开(公告)号：US20060123176A1

公开(公告)日：2006-06-08

申请号：US11163622

申请日：2005-10-25

申请人： Lars-Berno Fredriksson ,  Kent Lennartsson

发明人： Lars-Berno Fredriksson ,  Kent Lennartsson

IPC分类号： G06F13/14

CPC分类号： G06F13/4291 ,  H04L12/40013 ,  H04L27/2335 ,  H04L43/00 ,  H04L43/0823 ,  H04L43/106 ,  H04L2012/40215

摘要： A device suitable for use as a module in a Controller Area Network (CAN) system with a bus or connection includes relatively simple and inexpensive components, including an oscillator that generates a number of different frequencies in response to directions from a microcomputer. A CAN Controller receiving the frequencies is connected to the bus via a transceiver. The device has utility for verification and validation work in association with a CAN system.

摘要翻译： 适用于具有总线或连接的控制器局域网（CAN）系统中的模块的设备包括相对简单且便宜的组件，包括响应于来自微型计算机的方向产生多个不同频率的振荡器。 接收频率的CAN控制器通过收发器连接到总线。 该设备具有与CAN系统相关联的验证和验证工作的实用程序。

公开(公告)号：US06473469B1

公开(公告)日：2002-10-29

申请号：US09294088

申请日：1999-04-19

申请人： James R. Leitch

发明人： James R. Leitch

IPC分类号： H04L2720

CPC分类号： H04L27/2335 ,  H04L27/2057

摘要： A local area network is based on a ring of twisted pair cable links (UTP), each carrying at least 1.4 Mbps gross data rate. Each station on the network includes an encoder and a following station includes a decoder for PSK (phase shift keying) modulated serial data. The encoder uses an analog sine wave oscillator and inverter for generating antiphase analog sine wave signals at a carrier frequency and a switching circuit for selecting between the carrier signals according to the data signal to be transmitted. The decoder may use a simple integrator and comparator arrangement. The encoder and decoder may be provided in the form of an adapter circuit, such that a network based on optical fibre can be replaced by a network based on twisted pair cable using the same digital circuits. Generation of the PSK waveform by analog circuitry rather than digital synthesis reduces radio frequency emissions to a level suitable for use in an automotive audio/video communications network.

摘要翻译： 局域网基于一对双绞线电缆链路（UTP），每个端口的总数据速率至少为1.4 Mbps。 网络上的每个站包括编码器，后续站包括用于PSK（相移键控）调制串行数据的解码器。 编码器使用模拟正弦波振荡器和逆变器来产生载波频率的反相模拟正弦波信号和用于根据要发送的数据信号在载波信号之间进行选择的开关电路。 解码器可以使用简单的积分器和比较器装置。 编码器和解码器可以以适配器电路的形式提供，使得基于光纤的网络可以由使用相同数字电路的基于双绞线电缆的网络代替。 通过模拟电路而不是数字合成生成PSK波形将射频发射降低到适用于汽车音频/视频通信网络的水平。

公开(公告)号：US5585761A

公开(公告)日：1996-12-17

申请号：US152049

申请日：1993-11-12

申请人： Seppo E. M. Lamberg ,  Zhi C. Honkasalo

发明人： Seppo E. M. Lamberg ,  Zhi C. Honkasalo

IPC分类号： H04L27/22 ,  H04L27/233 ,  H04L27/18

CPC分类号： H04L27/2335

摘要： A method is disclosed of demodulating a signal (20) modulated by differential quadrature phase shift keying so that two bits of information are coded into each symbol period. The method comprises using a high frequency clock to determine the time taken (t.sub.1, t.sub.2, t.sub.3, t.sub.4), for the modulated signal to execute a predetermined number of cycles, such as 21, in the symbol period (T) and comparing the time thereby determined with the time (t.sub.o) of execution of the predetermined number of cycles for an unmodulated signal.

摘要翻译： 公开了一种解调通过差分正交相移键控调制的信号（20）的方法，使得两个比特的信息被编码到每个符号周期中。 该方法包括使用高频时钟来确定调制信号在符号周期（T）中执行预定数量的周期（例如21）所花费的时间（t1，t2，t3，t4），并比较时间 从而由对未调制信号执行预定数量的周期的时间（至）来确定。

公开(公告)号：US4799239A

公开(公告)日：1989-01-17

申请号：US856777

申请日：1986-04-28

申请人： Sheldon Pearlman ,  Anatoly Fridland ,  Gunther J. Martin

发明人： Sheldon Pearlman ,  Anatoly Fridland ,  Gunther J. Martin

IPC分类号： H04L27/233 ,  H04L27/14

CPC分类号： H04L27/2335

摘要： A system and process for receiving phase-coherent FSK signals having data and clock components which includes a plurality of subsystems and a means for carrying data among the subsystems. At least two of the subsystems are able to communicate by means of a transmitter in one of them and a receiver in the other. The receiver includes a demodulator for separating the data and clock components of the encoded phase-coherent FSK signals. The clock demodulator includes a first transition detector and a 90-degree phase shift circuit which both receive the encoded signal. A second transition detector receives the output of the phase shift or phase delay circuit. An OR gate receives the output of the first and second transition detectors to produce a four times clock signal. The data component of the phase-coherent FSK signal is recovered by either of two alternate circuits. The first circuit uses a shift register which examines at least four samples of data in conjunction with a pair of exclusive OR gates, a NOR gate, and a flip-flop. An alternate data component demodulator includes a first 90-degree phase delay circuit and an inverter both receiving the encoded data and transmitting it to a first exclusive OR gate. A second 90-degree phase delay circuit receives the output of the first exclusive OR gate. A second exclusive OR gate receives the outputs of both the second phase delay circuit and the first exclusive OR gate.

摘要翻译： 一种用于接收具有包括多个子系统的数据和时钟分量的相位相干FSK信号的系统和过程，以及用于在子系统之间传送数据的装置。 至少两个子系统能够通过其中一个中的发射机和另一个中的接收机进行通信。 接收机包括用于分离编码的相位相干FSK信号的数据和时钟分量的解调器。 时钟解调器包括第一转换检测器和接收编码信号的90度相移电路。 第二转换检测器接收相移或相位延迟电路的输出。 或门接收第一和第二转换检测器的输出以产生四倍时钟信号。 相位相干FSK信号的数据分量由两个交替电路之一恢复。 第一个电路使用一个移位寄存器，它与一对异或门，或非门和触发器一起检查至少四个数据采样。 备用数据分量解调器包括第一90度相位延迟电路和逆变器，两者接收编码数据并将其发送到第一异或门。 第二90度相位延迟电路接收第一异或门的输出。 第二异或门接收第二相位延迟电路和第一异或门的输出。

公开(公告)号：US4216543A

公开(公告)日：1980-08-05

申请号：US15014

申请日：1979-02-26

申请人： George C. Cagle ,  Roger A. Bloom

发明人： George C. Cagle ,  Roger A. Bloom

IPC分类号： H04L7/033 ,  H04L27/18 ,  H04L27/233 ,  H03D3/22

CPC分类号： H04L7/033 ,  H04L27/2335

摘要： Baud timing is derived from an AC signal having n half-cycles during each baud period, for use in demodulating a carrier signal bearing digital information via some predetermined variation in a characteristic of the carrier signal during each baud period, by converting the carrier signal characteristic variation to a DC signal, sampling the DC signal at the same point during each half-cycle of the AC signal, summing the samples corresponding to the same half-cycle of the AC signal within each sequence of AC signal half-cycles occurring over successive baud periods, there being n such sample totals, identifying the largest one of the n totals and sychronizing the baud timing signal to the AC half-cycle corresponding thereto.

摘要翻译： 在每个波特周期期间，从具有n个半周期的AC信号导出波形定时，用于通过在每个波特周期期间通过载波信号的特性经过一些预定变化来解调承载数字信息的载波信号，通过转换载波信号特性 对DC信号的变化，在AC信号的每个半周期期间在同一点对DC信号进行采样，将对应于相继的AC信号的相同半周期的采样相加，在连续发生的AC信号半周期的每个序列内 波特率周期，存在n个这样的样本总数，识别n个总计中的最大的一个，并将波特定时信号同步到与之对应的AC半周期。

公开(公告)号：US08472909B2

公开(公告)日：2013-06-25

申请号：US12993901

申请日：2009-05-20

申请人： Denis Noel

发明人： Denis Noel

IPC分类号： H04B1/10

CPC分类号： H04L27/1563 ,  H04L27/2335

摘要： The invention relates to a filter device (341, 342) for detecting and/or removing erroneous components like noise, deformations, glitch components or other errors in and/or from a signal, to a demodulation device using the filter device, to an information transmission system using the demodulation device and to a method for detecting a noise impulse in an input signal (Cα(t), Cα[k]). The filter device includes a summing element (510-51N, 610) connected to a correction element (540, 640). The summing element (510-51N, 610) sums the input signal (Cα(t), Cα[k]) within a reference interval (N) and the correction element (540, 640) verifies the summed input signal (IS[k]) with at least one signal condition (0, N+1, ΔCα[k]). Finally, the correction element (540, 640) outputs a predetermined signal (Cαα[k]) based on the result of the verification between the summed input signal (IS[k]) with at least one signal condition (0, N+1, ΔCα[k]). The foregoing filter device is able to remove noise from an input signal. This stabilizes the input signal against environmental influences occurring e.g. during signal transmission.

摘要翻译： 本发明涉及一种滤波器装置（341,342），用于将信号中的噪声，变形，毛刺分量或其他错误中的错误组件或使用该滤波器装置的解调装置检测和/或去除信息 使用解调装置的传输系统和用于检测输入信号（Calpha（t），Calpha [k]）中的噪声脉冲的方法。 滤波器装置包括连接到校正元件（540,640）的求和元件（510-51N，610）。 求和元件（510-51N，610）将参考间隔（N）内的输入信号（Calpha（t），Calpha [k]）相加，并且校正元件（540,640）验证求和的输入信号（IS [k ]）与至少一个信号条件（0，N + 1，DeltaCalpha [k]）。 最后，校正元件（540,640）基于加法输入信号（IS [k]）与至少一个信号条件（0，N + 1）之间的验证结果输出预定信号（Calphaalpha [k]） ，DeltaCalpha [k]）。 上述滤波器装置能够从输入信号中去除噪声。 这就稳定了输入信号，防止了环境影响。 在信号传输期间。

公开(公告)号：US08472569B2

公开(公告)日：2013-06-25

申请号：US12961271

申请日：2010-12-06

申请人： June Chul Roh ,  Srinath Hosur ,  Timothy M. Schmidl

发明人： June Chul Roh ,  Srinath Hosur ,  Timothy M. Schmidl

IPC分类号： H03D1/00 ,  H04L27/06

CPC分类号： H04L27/205 ,  H04L27/2335

摘要： Systems and methods for fine symbol timing estimation are disclosed herein. In one embodiment, a wireless receiver includes a differential detector, a correlator, a coarse symbol timing estimator, and a fine symbol timing estimator. The differential detector is configured to detect phase differences in a received preamble signal modulated using differential phase shift keying. The correlator is configured to correlate symbol values output by the differential detector against a reference sequence. The coarse symbol timing estimator is configured to generate a coarse symbol timing estimate, and to generate a coarse timing sample symbol index value corresponding to the coarse symbol timing estimate. The fine symbol timing estimator is configured to generate a fine symbol timing estimate that is more accurate than the coarse symbol timing estimate based on the coarse timing sample symbol index value and correlation samples at index values preceding and succeeding the coarse timing sample index value.

摘要翻译： 本文公开了用于精细符号定时估计的系统和方法。 在一个实施例中，无线接收机包括差分检测器，相关器，粗略符号定时估计器和精细符号定时估计器。 差分检测器被配置为检测使用差分相移键控调制的接收前导信号中的相位差。 相关器被配置为将由差分检测器输出的符号值与参考序列相关联。 粗略符号定时估计器被配置为产生粗略符号定时估计，并且生成与粗略符号定时估计对应的粗定时采样符号索引值。 精细符号定时估计器被配置为基于粗略定时样本符号索引值和在粗略定时样本索引值之前和之后的索引值处的相关样本，生成比粗略符号定时估计更精确的精细符号定时估计。

公开(公告)号：US08295404B1

公开(公告)日：2012-10-23

申请号：US12122013

申请日：2008-05-16

申请人： Paul J. Husted ,  Soner Ozgur

发明人： Paul J. Husted ,  Soner Ozgur

IPC分类号： H03D3/22

CPC分类号： H04L27/2071 ,  H04L27/2334 ,  H04L27/2335 ,  H04L27/2338 ,  H04L2027/0069

摘要： One embodiment of a DPSK receiver includes an ADC, a down-sampler, and a timing tracker. The ADC samples a received DPSK signal providing sub-samples of a digital signal. The timing tracker examines differences between amplitudes of currently selected sub-samples and sub-samples before and after the currently selected sub-samples. The differences may indicate a timing adjustment may be made to the digital signal. The timing tracker may change the timing of the digital signal by modifying the configuration of the down-sampler. Additionally, the timing tracker may also correct phase errors introduced by configuration changes of the down-sampler.

摘要翻译： DPSK接收机的一个实施例包括ADC，下采样器和定时跟踪器。 ADC对接收的DPSK信号进行采样，提供数字信号的子样本。 定时跟踪器检查当前选择的子样本之前和之后当前选择的子样本和子样本的幅度之间的差异。 差异可以指示可以对数字信号进行定时调整。 定时跟踪器可以通过修改下采样器的配置来改变数字信号的定时。 此外，定时跟踪器还可以校正由下采样器的配置变化引入的相位误差。