公开(公告)号：US06438737B1

公开(公告)日：2002-08-20

申请号：US09505059

申请日：2000-02-15

申请人： John Morelli ,  H. Richard Kendall

发明人： John Morelli ,  H. Richard Kendall

IPC分类号： G06F1750

CPC分类号： G06F15/7867

摘要： A system is disclosed including a reconfigurable logic circuit having programmable logic, a first memory, and a second memory. The first memory stores a number of logic designs each operable to configure the programmable logic. Also included is a computer coupled to the reconfigurable logic circuit that concurrently executes one or more application programs and an interface program. The application programs generate a number of requests to utilize the reconfigurable logic circuit and the interface program responds to the requests by opening a number of coexisting program interfaces. These interfaces each correspond to an instance of one of the logic designs stored in the first memory. The reconfigurable logic circuit is responsive to the interface program to provide a number of interface buffers in the second memory that each belong to a corresponding one of the interfaces and are each operable to store data passing between the computer and the reconfigurable logic circuit.

摘要翻译： 公开了一种包括具有可编程逻辑的可重构逻辑电路，第一存储器和第二存储器的系统。 第一存储器存储多个可用于配置可编程逻辑的逻辑设计。 还包括耦合到可重配置逻辑电路的计算机，其同时执行一个或多个应用程序和接口程序。 应用程序产生许多请求以利用可重构逻辑电路，并且接口程序通过打开多个共存程序接口来响应请求。 这些接口各自对应于存储在第一存储器中的逻辑设计之一的实例。 可重构逻辑电路响应于接口程序以在第二存储器中提供多个接口缓冲器，每个接口缓冲器各自属于对应的一个接口，并且每个可操作以存储在计算机和可重配置逻辑电路之间通过的数据。