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    FLASH MEMORY DEVICES WITH SELECTIVE BIT LINE DISCHARGE PATHS AND METHODS OF OPERATING THE SAME
    1.
    发明申请
    FLASH MEMORY DEVICES WITH SELECTIVE BIT LINE DISCHARGE PATHS AND METHODS OF OPERATING THE SAME 有权
    具有选择位线排放板的闪存存储器件及其操作方法

    公开(公告)号：US20110216602A1

    公开(公告)日：2011-09-08

    申请号：US12813050

    申请日：2010-06-10

    申请人： Euido Kim ,  Bong Yong Lee ,  Haebum Lee ,  Sang-Youl Kwon ,  Jin-Young Kim ,  Hye Yeon Yun ,  Houng-kuk Jang

    发明人： Euido Kim ,  Bong Yong Lee ,  Haebum Lee ,  Sang-Youl Kwon ,  Jin-Young Kim ,  Hye Yeon Yun ,  Houng-kuk Jang

    IPC分类号： G11C16/06

    CPC分类号： G11C16/06

    摘要： Provided is a flash memory device that can include a memory cell configured to store data, a local bit line that is connected to the memory cell, a global bit line that is connected to the local bit line, a discharge transistor that is connected to the global bit line, and that is configured to selectively connect the global bit line to a reference level responsive to a discharge control signal, and a discharge control circuit, that is connected to the discharge transistor via the discharge control signal, and that is configured to selectively disable the discharge transistor during an erase interval occurring before a verify interval of an erase verification operation carried out by the flash memory device.

    摘要翻译： 提供了一种闪存器件，其可以包括被配置为存储数据的存储器单元，连接到存储单元的局部位线，连接到本地位线的全局位线，连接到本地位线的放电晶体管 全局位线，并且被配置为响应于放电控制信号选择性地将全局位线连接到参考电平;以及放电控制电路，其通过放电控制信号连接到放电晶体管，并且被配置为 在由闪速存储器件执行的擦除验证操作的验证间隔之前的擦除间隔期间，选择性地禁用放电晶体管。

    Flash memory devices with selective bit line discharge paths and methods of operating the same
    2.
    发明授权
    Flash memory devices with selective bit line discharge paths and methods of operating the same 有权
    具有选择性位线放电路径的闪存器件及其操作方法

    公开(公告)号：US08363482B2

    公开(公告)日：2013-01-29

    申请号：US12813050

    申请日：2010-06-10

    申请人： Euido Kim ,  BongYong Lee ,  Haebum Lee ,  Sang-Youl Kwon ,  Jin-Young Kim ,  Hye Yeon Yun ,  Houng-kuk Jang

    发明人： Euido Kim ,  BongYong Lee ,  Haebum Lee ,  Sang-Youl Kwon ,  Jin-Young Kim ,  Hye Yeon Yun ,  Houng-kuk Jang

    IPC分类号： G11C11/34

    CPC分类号： G11C16/06

    摘要： Provided is a flash memory device that can include a memory cell configured to store data, a local bit line that is connected to the memory cell, a global bit line that is connected to the local bit line, a discharge transistor that is connected to the global bit line, and that is configured to selectively connect the global bit line to a reference level responsive to a discharge control signal, and a discharge control circuit, that is connected to the discharge transistor via the discharge control signal, and that is configured to selectively disable the discharge transistor during an erase interval occurring before a verify interval of an erase verification operation carried out by the flash memory device.

    摘要翻译： 提供了一种闪存器件，其可以包括被配置为存储数据的存储器单元，连接到存储单元的局部位线，连接到本地位线的全局位线，连接到本地位线的放电晶体管 全局位线，并且被配置为响应于放电控制信号选择性地将全局位线连接到参考电平;以及放电控制电路，其通过放电控制信号连接到放电晶体管，并且被配置为 在由闪速存储器件执行的擦除验证操作的验证间隔之前的擦除间隔期间，选择性地禁用放电晶体管。