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公开(公告)号：US12073898B2
公开(公告)日：2024-08-27
申请号：US18361132
申请日：2023-07-28
发明人： Eun-Ji Kim , Jung-June Park , Jeong-Don Ihm , Byung-Hoon Jeong , Young-Don Choi
CPC分类号： G11C29/025 , G11C5/063 , G11C7/1048 , G11C7/1057 , G11C7/1084 , G11C16/06 , G11C16/102 , G11C16/26 , G11C29/022 , G11C29/028
摘要： A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
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公开(公告)号：US12020753B2
公开(公告)日：2024-06-25
申请号：US18359764
申请日：2023-07-26
申请人： Kioxia Corporation
发明人： Naoya Tokiwa
CPC分类号： G11C16/16 , G11C16/0466 , G11C16/0483 , G11C16/26 , G11C16/3445 , G11C16/06 , G11C16/08 , G11C16/10
摘要： A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.
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公开(公告)号：US12002513B2
公开(公告)日：2024-06-04
申请号：US17567401
申请日：2022-01-03
申请人： Rambus Inc.
发明人： Gary B. Bronner , Brent Steven Haukness , Mark A. Horowitz , Mark D. Kellam , Fariborz Assaderaghi
IPC分类号： G11C16/06 , G11C13/00 , G11C16/26 , G11C7/04 , H01L21/324
CPC分类号： G11C16/06 , G11C13/0002 , G11C13/0033 , G11C13/0035 , G11C16/26 , G11C7/04 , H01L21/324
摘要： Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.
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4.发明公开公开(公告)号：US20240176747A1
公开(公告)日：2024-05-30
申请号：US18184241
申请日：2023-03-15
申请人： SK hynix Inc.
发明人： Hoe Seung JUNG , Do Hyung KIM , Chi Heon KIM , Joo Young LEE
IPC分类号： G06F12/10
摘要： A storage device may load, between a first time point at which information on candidate memory regions among a plurality of memory regions is started to be sent to an external device and a second time point at which a command requesting a map segment for a target memory region among the plurality of memory regions is received from the external device, all or a part of map segments corresponding to the candidate memory regions into a buffer.
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公开(公告)号：US11990900B2
公开(公告)日：2024-05-21
申请号：US17483473
申请日：2021-09-23
发明人： Huangpeng Zhang , Shiyang Yang
CPC分类号： H03K19/0005 , G11C16/0483 , G11C16/06 , G11C29/50008
摘要： In certain aspects, a circuit for ZQ resistor calibration can include a first input configured to receive a first default configuration. The circuit can also include a second input configured to receive a first calibration value based on a first comparison. The circuit can further include a first output configured to provide a first resistor code for a first resistor category. The circuit can additionally include a second output configured to provide a second resistor code for a second resistor category different from the first resistor category. The circuit can also include a first logic circuit configured to receive a signal from the first input and a signal from the second input, and provide a signal to the first output. The signal to the first output can include the first resistor code. The first resistor code can be different from the second resistor code.
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公开(公告)号：US20240105238A1
公开(公告)日：2024-03-28
申请号：US18528395
申请日：2023-12-04
发明人： Hang Song , Daesik Song , Lin Yang
CPC分类号： G11C7/1048 , G11C16/06 , G11C2207/2254
摘要： In certain aspects, a circuit for multi-mode calibration can include a resistor input. The circuit can also include a first comparator connected to the resistor input and to a first plurality of voltage sources. The circuit can also include a first pull-up driver. The circuit can further include a logic pull-up code generator to calibrate the first pull-up driver. The circuit can additionally include a replica of the first pull-up driver. The circuit can also include a first pull-down driver and a second comparator connected to the replica, the first pull-down driver, and a second plurality of voltage sources. The second comparator can compare a voltage of a middle point between the first pull-down driver and the second pull-up driver to one of the second plurality of voltage sources. The circuit can further include a logic pull-down code generator.
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公开(公告)号：US20240105237A1
公开(公告)日：2024-03-28
申请号：US18528339
申请日：2023-12-04
发明人： Hang Song , Daesik Song , Lin Yang
CPC分类号： G11C7/1048 , G11C16/06 , G11C2207/2254
摘要： In certain aspects, a circuit for multi-mode calibration can include a resistor input. The circuit can also include a first comparator connected to the resistor input and to a first plurality of voltage sources. The circuit can also include a first pull-up driver. The circuit can further include a logic pull-up code generator to calibrate the first pull-up driver. The circuit can additionally include a replica of the first pull-up driver. The circuit can also include a first pull-down driver and a second comparator connected to the replica, the first pull-down driver, and a second plurality of voltage sources. The second comparator can compare a voltage of a middle point between the first pull-down driver and the second pull-up driver to one of the second plurality of voltage sources. The circuit can further include a logic pull-down code generator.
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公开(公告)号：US20240088152A1
公开(公告)日：2024-03-14
申请号：US18362316
申请日：2023-07-31
申请人： Kioxia Corporation
发明人： Tomoaki SHINO , Mitsuhiro NOGUCHI , Takayuki TOBA
IPC分类号： H01L27/092 , G11C16/04 , G11C16/06 , H01L21/265 , H01L29/78 , H10B41/27 , H10B41/35 , H10B41/41
CPC分类号： H01L27/0922 , G11C16/0483 , G11C16/06 , H01L21/26586 , H01L27/0928 , H01L29/7833 , H10B41/27 , H10B41/35 , H10B41/41
摘要： A semiconductor device of an embodiment includes N-wells and P-wells extending in a first direction and alternately arranged in a second direction orthogonal to the first direction; and a dummy gate formed above the N-wells and the P-wells so as to extend across at least one boundary between an N-well and a P-well that are adjacent to each other, the dummy gate being not connected to a wire, in which the dummy gate is formed in a region other than an end portion in the first direction of, among the N-wells and the P-wells, a well that has a width smaller than a predetermined threshold in the second direction.
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公开(公告)号：US11875864B2
公开(公告)日：2024-01-16
申请号：US17499571
申请日：2021-10-12
申请人： PetaIO Inc.
发明人： Naveen Kumar , Chengxu Zhang , Seok Lee , LingQi Zeng
CPC分类号： G11C16/3495 , G11C16/06 , G11C16/102 , G11C16/28 , G11C29/42
摘要： A storage device includes 3D NAND including layers of multi-level cells. When a shutdown command is received, whether a block is partially written is evaluated. If so, dummy lines are written after the last written wordline of the block. Partially written blocks may be those having a fill percentage less than a threshold. The threshold may be a function of the PEC count of the block. If a maximum retention time is exceeded by data stored in a partially written block, dummy lines may also be written to the block.
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公开(公告)号：US20230301086A1
公开(公告)日：2023-09-21
申请号：US18138820
申请日：2023-04-25
申请人： Kioxia Corporation
发明人： Koichiro YAMAGUCHI
CPC分类号： H10B41/41 , G11C16/0483 , G11C16/06 , G11C16/26 , G11C16/34 , G11C16/3436 , H10B41/35 , H10B43/35
摘要： A method of controlling a memory device includes receiving a write instruction; starting a write operation to a first address in response to the write instruction; receiving a first read instruction of the first address; suspending the write operation; and applying a read voltage to a word line corresponding to the first address in a first read operation in response to the first read instruction. The method further includes resuming the write operation is after applying the read voltage; receiving a second read instruction after applying the read voltage; and outputting read data from a data register in response to the second read instruction during a period starting at resuming the write operation and ending at completion of the write operation.
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