公开(公告)号：US09014955B2

公开(公告)日：2015-04-21

申请号：US14233409

申请日：2012-06-21

申请人： Hajime Sakakibara ,  Shigeki Nishimura ,  Masayuki Jinno ,  Hirofumi Ogami ,  Makoto Senga

发明人： Hajime Sakakibara ,  Shigeki Nishimura ,  Masayuki Jinno ,  Hirofumi Ogami ,  Makoto Senga

IPC分类号： G08G1/00 ,  G08G1/01

CPC分类号： G08G1/0116 ,  G08G1/0133 ,  G08G1/0141

摘要： This traffic simulator is provided with a simulator engine unit for performing computation on the basis of a formula representing a movement model for a vehicle, a traffic volume calculation unit for calculating a generated traffic volume and a removed traffic volume on the basis of a given OD traffic volume, an estimated congestion length calculation unit for calculating (estimating) an estimated congestion length for each link on the basis of the calculated traffic volume thereof, an origin and destination generation unit for generating an origin traffic volume and an destination traffic volume to adjust the estimated congestion length on the basis of the difference between the estimated congestion length and the measured congestion length, a storage unit for storing predetermined information, and an evaluation condition setting unit for setting evaluation conditions for evaluating the traffic various quantities metrics.

摘要翻译： 该交通模拟器具有模拟器引擎单元，用于基于表示车辆的移动模型的公式进行计算，用于计算所生成的交通量的交通量计算单元和基于给定OD的移除的交通量 估计拥堵长度计算单元，用于基于计算出的业务量来计算（估计）每个链路的估计拥塞长度;生成原始业务量的源和目的地生成单元和用于调整的目的地业务量 基于所估计的拥塞长度和所测量的拥塞长度之间的差异来估计拥塞长度，用于存储预定信息的存储单元，以及用于设置用于评估业务各种量度量的评估条件的评估条件设置单元。

公开(公告)号：US20140149029A1

公开(公告)日：2014-05-29

申请号：US14233409

申请日：2012-06-21

申请人： Hajime Sakakibara ,  Shigeki Nishimura ,  Masayuki Jinno ,  Hirofumi Ogami ,  Makoto Senga

发明人： Hajime Sakakibara ,  Shigeki Nishimura ,  Masayuki Jinno ,  Hirofumi Ogami ,  Makoto Senga

IPC分类号： G08G1/00

CPC分类号： G08G1/0116 ,  G08G1/0133 ,  G08G1/0141

摘要： This traffic simulator is provided with a simulator engine unit for performing computation on the basis of a formula representing a movement model for a vehicle, a traffic volume calculation unit for calculating a generated traffic volume and a removed traffic volume on the basis of a given OD traffic volume, an estimated congestion length calculation unit for calculating (estimating) an estimated congestion length for each link on the basis of the calculated traffic volume thereof, an origin and destination generation unit for generating an origin traffic volume and an destination traffic volume to adjust the estimated congestion length on the basis of the difference between the estimated congestion length and the measured congestion length, a storage unit for storing predetermined information, and an evaluation condition setting unit for setting evaluation conditions for evaluating the traffic various quantities metrics.

摘要翻译： 该交通模拟器具有模拟器引擎单元，用于基于表示车辆的移动模型的公式进行计算，用于计算所生成的交通量的交通量计算单元和基于给定OD的移除的交通量 估计拥堵长度计算单元，用于基于计算出的业务量来计算（估计）每个链路的估计拥塞长度;生成原始业务量的源和目的地生成单元和用于调整的目的地业务量 基于所估计的拥塞长度和所测量的拥塞长度之间的差异来估计拥塞长度，用于存储预定信息的存储单元，以及用于设置用于评估业务各种量度量的评估条件的评估条件设置单元。

公开(公告)号：US4788679A

公开(公告)日：1988-11-29

申请号：US083646

申请日：1987-08-10

申请人： Hideki Kataoka ,  Tatsuro Takahashi ,  Shiro Kikuchi ,  Naoaki Yamanaka ,  Hajime Sakakibara ,  Miki Hirano

发明人： Hideki Kataoka ,  Tatsuro Takahashi ,  Shiro Kikuchi ,  Naoaki Yamanaka ,  Hajime Sakakibara ,  Miki Hirano

IPC分类号： H04L12/933 ,  H04L12/935 ,  H04J3/26

CPC分类号： H04L49/103 ,  H04L49/1515 ,  H04L49/30

摘要： A packet switch has pluralities of incoming and outgoing trunks, a data memory accessible from them in common, and FIFO memories each provided in each of input and output circuits. Data from the incoming trunks is written into and read out from the buffer memory for transfer to the outgoing trunks, on a time-shared basis, to perform packet switching between trunks of different data transfer rates. Furthermore, the packet switch has an arbiter for detecting process requests from the input circuits and an arbiter for detecting process requests from the output circuits, so that priority control is effected for servicing the requests. As a result, dynamic allocation of access to the buffer memory to the input and output circuits is permitted.

摘要翻译： 分组交换机具有多个入站和出站中继线，可共同访问的数据存储器以及每个输入和输出电路中各提供的FIFO存储器。 来自传入干线的数据被写入并从缓冲存储器中读出，以便在时间共享的基础上传送到输出中继线，以在不同数据传输速率的干线之间执行分组交换。 此外，分组交换机具有用于检测来自输入电路的处理请求的仲裁器和用于检测来自输出电路的处理请求的仲裁器，从而对服务请求进行优先级控制。 结果，允许对输入和输出电路的缓冲存储器的访问的动态分配。