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公开(公告)号：US08547169B2
公开(公告)日：2013-10-01
申请号：US13104899
申请日：2011-05-10
IPC分类号： H03K5/00
CPC分类号： H03H7/0153 , H03K5/24
摘要： A system and method are disclosed for reducing the kickback disturbance in an electronic circuit. The system is based on the coupling of a programmable noise filter between bias blocks. In one embodiment the programmable noise filter includes capacitors, resisters and switches and forms a C-R-C circuit structure. By selecting the resistance and capacitance values and the status of the switches, the performance of the programmable noise filter is determined. Also disclosed is a system and method to reduce kickback disturbances comprising N+1 bias blocks, N programmable noise filters, and a bias reference generator, wherein N is equal to or greater than one.
摘要翻译： 公开了一种用于减小电子电路中的反冲扰的系统和方法。 该系统基于偏置块之间的可编程噪声滤波器的耦合。 在一个实施例中，可编程噪声滤波器包括电容器，电阻器和开关，并形成C-R-C电路结构。 通过选择电阻和电容值以及开关的状态，确定可编程噪声滤波器的性能。 还公开了一种减少包括N + 1个偏置块，N个可编程噪声滤波器和偏置参考发生器的反冲扰的系统和方法，其中N等于或大于1。
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公开(公告)号：US07898309B1
公开(公告)日：2011-03-01
申请号：US12466288
申请日：2009-05-14
申请人： Hakan Dogan
发明人： Hakan Dogan
CPC分类号： H03K5/1565
摘要： Providing duty cycle correction can include determining whether a clock signal has a duty cycle greater than 50% based on averaging the clock signal and comparing that averaged clock signal to ½ VDD. When the duty cycle is greater than 50%, the clock signal can be selected. When the duty cycle is less than 50%, the inverted clock signal can be selected. Thus, a duty cycle corrected clock signal can be generated based on the clock signal or the inverted clock signal. Notably, a duty cycle control signal can be adjusted based on comparisons of an averaged, duty cycle corrected clock signal and predetermined low/high voltage ranges. Components performing comparing functions can be strobed based on a count performed on the clock signal.
摘要翻译： 提供占空比校正可以包括基于平均时钟信号来确定时钟信号是否具有大于50％的占空比，并将该平均时钟信号与½VDD进行比较。 当占空比大于50％时，可以选择时钟信号。 当占空比小于50％时，可以选择反相时钟信号。 因此，可以基于时钟信号或反相时钟信号产生占空比校正时钟信号。 值得注意的是，可以基于平均的占空比校正时钟信号和预定的低/高电压范围的比较来调整占空比控制信号。 可以基于对时钟信号执行的计数来选择执行比较功能的组件。
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公开(公告)号：US20120286856A1
公开(公告)日：2012-11-15
申请号：US13104899
申请日：2011-05-10
IPC分类号： H04B15/02
CPC分类号： H03H7/0153 , H03K5/24
摘要： A system and method are disclosed for reducing the kickback disturbance in an electronic circuit. The system is based on the coupling of a programmable noise filter between bias blocks. In one embodiment the programmable noise filter includes capacitors, resisters and switches and forms a C-R-C circuit structure. By selecting the resistance and capacitance values and the status of the switches, the performance of the programmable noise filter is determined. Also disclosed is a system and method to reduce kickback disturbances comprising N+1 bias blocks, N programmable noise filters, and a bias reference generator, wherein N is equal to or greater than one.
摘要翻译： 公开了一种用于减小电子电路中的反冲扰的系统和方法。 该系统基于偏置块之间的可编程噪声滤波器的耦合。 在一个实施例中，可编程噪声滤波器包括电容器，电阻器和开关，并形成C-R-C电路结构。 通过选择电阻和电容值以及开关的状态，确定可编程噪声滤波器的性能。 还公开了一种减少包括N + 1个偏置块，N个可编程噪声滤波器和偏置参考发生器的反冲扰的系统和方法，其中N等于或大于1。
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公开(公告)号：US20130203369A1
公开(公告)日：2013-08-08
申请号：US13368009
申请日：2012-02-07
IPC分类号： H04B1/10
摘要： A mechanism is disclosed for improving the performance of a coexisting radio by integrating a notch filter into an LNA of a first coexisting radio of two or more coexisting radios. The notch filter may be a differential circuit or a single-ended circuit. The single-ended circuit filters common mode signals. In one embodiment, the first coexisting radio has a carrier frequency that is in 2.4 GHz ISM frequency band and one of the other two or more coexisting radios has a carrier frequency that is in 1.9 GHz cellular band.
摘要翻译： 公开了一种用于通过将陷波滤波器集成到两个或更多个共存无线电的第一共存无线电的LNA中来提高共存无线电的性能的机制。 陷波滤波器可以是差分电路或单端电路。 单端电路对共模信号进行滤波。 在一个实施例中，第一共存无线电装置具有在2.4GHz ISM频带中的载波频率，而另外两个或更多个共存无线电中的一个具有1.9GHz蜂窝频带的载波频率。
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