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1.发明授权Duty cycle correction circuits having short locking times that are relatively insensitive to temperature changes 有权具有对温度变化相对不敏感的短锁定时间的占空比校正电路公开(公告)号：US07990195B2
公开(公告)日：2011-08-02
申请号：US12603717
申请日：2009-10-22
申请人： Harmendra Panditd , Su Ho Kim , Won Lee , Alex Joo , Kwan Yeob Chae , Jong-Ryun Choi
发明人： Harmendra Panditd , Su Ho Kim , Won Lee , Alex Joo , Kwan Yeob Chae , Jong-Ryun Choi
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit includes a duty cycle correction portion that is configured to output a correction signal that is obtained by correcting a duty cycle of an input signal and to output a delayed signal that is obtained by delaying the correction signal, a complementary portion that is configured to output a complementary signal that is the complement of the delayed signal, and a phase interpolator that is configured to phase interpolate the complementary signal and the correction signal.
摘要翻译： 占空比校正电路包括占空比校正部分，其被配置为输出通过校正输入信号的占空比获得的校正信号，并输出通过延迟校正信号而获得的延迟信号;互补部分， 被配置为输出作为所述延迟信号的互补的互补信号，以及相位插值器，被配置为相互插补所述互补信号和所述校正信号。
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2.发明申请DUTY CYCLE CORRECTION CIRCUITS HAVING SHORT LOCKING TIMES THAT ARE RELATIVELY INSENSITIVE TO TEMPERATURE CHANGES 有权具有相对温度变化敏感的短暂锁定时间的周期校正电路公开(公告)号：US20100097112A1
公开(公告)日：2010-04-22
申请号：US12603717
申请日：2009-10-22
申请人： Harmendra Panditd , Su Ho Kim , Won Lee , Alex Joo , Kwan Yeob Chae , Jong-Ryun Choi
发明人： Harmendra Panditd , Su Ho Kim , Won Lee , Alex Joo , Kwan Yeob Chae , Jong-Ryun Choi
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit includes a duty cycle correction portion that is configured to output a correction signal that is obtained by correcting a duty cycle of an input signal and to output a delayed signal that is obtained by delaying the correction signal, a complementary portion that is configured to output a complementary signal that is the complement of the delayed signal, and a phase interpolator that is configured to phase interpolate the complementary signal and the correction signal.
摘要翻译： 占空比校正电路包括占空比校正部分，其被配置为输出通过校正输入信号的占空比获得的校正信号，并输出通过延迟校正信号而获得的延迟信号;互补部分， 被配置为输出作为所述延迟信号的互补的互补信号，以及相位插值器，被配置为相互插补所述互补信号和所述校正信号。
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