Abstract:
A duty cycle correction circuit includes a duty cycle correction portion that is configured to output a correction signal that is obtained by correcting a duty cycle of an input signal and to output a delayed signal that is obtained by delaying the correction signal, a complementary portion that is configured to output a complementary signal that is the complement of the delayed signal, and a phase interpolator that is configured to phase interpolate the complementary signal and the correction signal.
Abstract:
A delay locked loop controls a plurality of delay blocks included in a delay line and thus generate a plurality of clock signals which have a frequency obtained by multiplying a frequency of a reference clock signal, an accurate phase delay, and a constant duty cycle. The delay locked loop calculates an initial delay value and applies it to the delay blocks, thereby preventing harmonic locking and reducing locking time.
Abstract:
A delay locked loop is provided. The delay locked loop controls the number of delay cells that delay the phase of an input clock during a locking operation and controls a phase delay value of at least one delay cell among a plurality of delay cells after the locking operation is completed.
Abstract:
A delay locked loop controls a plurality of delay blocks included in a delay line and thus generate a plurality of clock signals which have a frequency obtained by multiplying a frequency of a reference clock signal, an accurate phase delay, and a constant duty cycle. The delay locked loop calculates an initial delay value and applies it to the delay blocks, thereby preventing harmonic locking and reducing locking time.
Abstract:
A delay locked loop is provided. The delay locked loop controls the number of delay cells that delay the phase of an input clock during a locking operation and controls a phase delay value of at least one delay cell among a plurality of delay cells after the locking operation is completed.
Abstract:
A duty cycle correction circuit includes a duty cycle correction portion that is configured to output a correction signal that is obtained by correcting a duty cycle of an input signal and to output a delayed signal that is obtained by delaying the correction signal, a complementary portion that is configured to output a complementary signal that is the complement of the delayed signal, and a phase interpolator that is configured to phase interpolate the complementary signal and the correction signal.