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1.发明授权Duty cycle correction circuits having short locking times that are relatively insensitive to temperature changes 有权具有对温度变化相对不敏感的短锁定时间的占空比校正电路公开(公告)号：US07990195B2
公开(公告)日：2011-08-02
申请号：US12603717
申请日：2009-10-22
Applicant: Harmendra Panditd , Su Ho Kim , Won Lee , Alex Joo , Kwan Yeob Chae , Jong-Ryun Choi
Inventor： Harmendra Panditd , Su Ho Kim , Won Lee , Alex Joo , Kwan Yeob Chae , Jong-Ryun Choi
IPC: H03K3/017
CPC classification number: H03K5/1565
Abstract: A duty cycle correction circuit includes a duty cycle correction portion that is configured to output a correction signal that is obtained by correcting a duty cycle of an input signal and to output a delayed signal that is obtained by delaying the correction signal, a complementary portion that is configured to output a complementary signal that is the complement of the delayed signal, and a phase interpolator that is configured to phase interpolate the complementary signal and the correction signal.
Abstract translation: 占空比校正电路包括占空比校正部分，其被配置为输出通过校正输入信号的占空比获得的校正信号，并输出通过延迟校正信号而获得的延迟信号;互补部分， 被配置为输出作为所述延迟信号的互补的互补信号，以及相位插值器，被配置为相互插补所述互补信号和所述校正信号。
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Patent Agency Ranking
2.发明授权Delay locked loop, electronic device including the same, and method of operating the same 有权延迟锁定环，包括相同的电子设备及其操作方法公开(公告)号：US08049543B2
公开(公告)日：2011-11-01
申请号：US12592753
申请日：2009-12-02
Applicant: Hee Chai Kang , Kyeong Ho Ryu , Seong Ook Jung , Won Lee , Dong Hwan Lee , Alex Joo , Jong-Ryun Choi
Inventor： Hee Chai Kang , Kyeong Ho Ryu , Seong Ook Jung , Won Lee , Dong Hwan Lee , Alex Joo , Jong-Ryun Choi
IPC: H03L7/06
CPC classification number: H03L7/0814 , H03K5/00006 , H03K5/133 , H03K2005/00058 , H03L7/07 , H03L7/0995 , H03L7/10
Abstract: A delay locked loop controls a plurality of delay blocks included in a delay line and thus generate a plurality of clock signals which have a frequency obtained by multiplying a frequency of a reference clock signal, an accurate phase delay, and a constant duty cycle. The delay locked loop calculates an initial delay value and applies it to the delay blocks, thereby preventing harmonic locking and reducing locking time.
Abstract translation: 延迟锁定环控制包括在延迟线中的多个延迟块，从而产生具有通过将参考时钟信号的频率，精确相位延迟和恒定占空比相乘而获得的频率的多个时钟信号。 延迟锁定环路计算初始延迟值并将其应用于延迟块，从而防止谐波锁定并减少锁定时间。
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公开(公告)号：US20100219867A1
公开(公告)日：2010-09-02
申请号：US12659010
申请日：2010-02-23
Applicant: Jong-Ryun Choi , Dong Hwan Lee , Su Ho Kim , Won Lee , Alex Joo , Ji Hun Oh
Inventor： Jong-Ryun Choi , Dong Hwan Lee , Su Ho Kim , Won Lee , Alex Joo , Ji Hun Oh
IPC: H03L7/06
CPC classification number: H03L7/0814 , H03L7/0805 , H03L7/0818 , H03L7/10
Abstract: A delay locked loop is provided. The delay locked loop controls the number of delay cells that delay the phase of an input clock during a locking operation and controls a phase delay value of at least one delay cell among a plurality of delay cells after the locking operation is completed.
Abstract translation: 提供延迟锁定环。 延迟锁定环控制在锁定操作期间延迟输入时钟的相位的延迟单元的数量，并且在锁定操作完成之后控制多个延迟单元中的至少一个延迟单元的相位延迟值。
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4.发明申请Delay locked loop, electronic device including the same, and method of operating the same 有权延迟锁定环，包括相同的电子设备及其操作方法公开(公告)号：US20100194456A1
公开(公告)日：2010-08-05
申请号：US12592753
申请日：2009-12-02
Applicant: Hee Chai Kang , Kyeong Ho Ryu , Seong Ook Jung , Won Lee , Dong Hwan Lee , Alex Joo , Jong Ryun Choi
Inventor： Hee Chai Kang , Kyeong Ho Ryu , Seong Ook Jung , Won Lee , Dong Hwan Lee , Alex Joo , Jong Ryun Choi
IPC: H03L7/06
CPC classification number: H03L7/0814 , H03K5/00006 , H03K5/133 , H03K2005/00058 , H03L7/07 , H03L7/0995 , H03L7/10
Abstract: A delay locked loop controls a plurality of delay blocks included in a delay line and thus generate a plurality of clock signals which have a frequency obtained by multiplying a frequency of a reference clock signal, an accurate phase delay, and a constant duty cycle. The delay locked loop calculates an initial delay value and applies it to the delay blocks, thereby preventing harmonic locking and reducing locking time.
Abstract translation: 延迟锁定环控制包括在延迟线中的多个延迟块，从而产生具有通过将参考时钟信号的频率，精确相位延迟和恒定占空比相乘而获得的频率的多个时钟信号。 延迟锁定环路计算初始延迟值并将其应用于延迟块，从而防止谐波锁定并减少锁定时间。
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公开(公告)号：US08283958B2
公开(公告)日：2012-10-09
申请号：US12659010
申请日：2010-02-23
Applicant: Jong-Ryun Choi , Dong Hwan Lee , Su Ho Kim , Won Lee , Alex Joo , Ji Hun Oh
Inventor： Jong-Ryun Choi , Dong Hwan Lee , Su Ho Kim , Won Lee , Alex Joo , Ji Hun Oh
IPC: H03L7/06
CPC classification number: H03L7/0814 , H03L7/0805 , H03L7/0818 , H03L7/10
Abstract: A delay locked loop is provided. The delay locked loop controls the number of delay cells that delay the phase of an input clock during a locking operation and controls a phase delay value of at least one delay cell among a plurality of delay cells after the locking operation is completed.
Abstract translation: 提供延迟锁定环。 延迟锁定环控制在锁定操作期间延迟输入时钟的相位的延迟单元的数量，并且在锁定操作完成之后控制多个延迟单元中的至少一个延迟单元的相位延迟值。
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6.发明申请DUTY CYCLE CORRECTION CIRCUITS HAVING SHORT LOCKING TIMES THAT ARE RELATIVELY INSENSITIVE TO TEMPERATURE CHANGES 有权具有相对温度变化敏感的短暂锁定时间的周期校正电路公开(公告)号：US20100097112A1
公开(公告)日：2010-04-22
申请号：US12603717
申请日：2009-10-22
Applicant: Harmendra Panditd , Su Ho Kim , Won Lee , Alex Joo , Kwan Yeob Chae , Jong-Ryun Choi
Inventor： Harmendra Panditd , Su Ho Kim , Won Lee , Alex Joo , Kwan Yeob Chae , Jong-Ryun Choi
IPC: H03K3/017
CPC classification number: H03K5/1565
Abstract: A duty cycle correction circuit includes a duty cycle correction portion that is configured to output a correction signal that is obtained by correcting a duty cycle of an input signal and to output a delayed signal that is obtained by delaying the correction signal, a complementary portion that is configured to output a complementary signal that is the complement of the delayed signal, and a phase interpolator that is configured to phase interpolate the complementary signal and the correction signal.
Abstract translation: 占空比校正电路包括占空比校正部分，其被配置为输出通过校正输入信号的占空比获得的校正信号，并输出通过延迟校正信号而获得的延迟信号;互补部分， 被配置为输出作为所述延迟信号的互补的互补信号，以及相位插值器，被配置为相互插补所述互补信号和所述校正信号。
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