公开(公告)号：US08495539B1

公开(公告)日：2013-07-23

申请号：US13347301

申请日：2012-01-10

申请人： Valeria Mihalache ,  Kumar Deepak ,  Hem C. Neema ,  Sonal Santan

发明人： Valeria Mihalache ,  Kumar Deepak ,  Hem C. Neema ,  Sonal Santan

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method for compiling an HDL specification for simulation includes elaborating the HDL specification and determining singly-driven and multiply-driven nets of the elaborated circuit design. For each singly-driven net, a respective memory location is assigned to store a value of a corresponding driver of the net at runtime. For each multiply-driven net, a contiguous block of memory is assigned to store values of corresponding drivers of the net at runtime. For mixed language designs, this contiguous block contains values for drivers from all HDL languages involved. Simulation code that models the circuit design is generated. For each singly-driven net, the simulation code is configured to store a value of the corresponding driver of the singly-driven net in the respective memory location. For each multiply-driven net, the simulation code is configured to store the values of the corresponding drivers in the assigned block of memory. The generated simulation code is stored.

摘要翻译： 用于编译用于模拟的HDL规范的方法包括详细描述HDL规范并确定精心制作的电路设计的单驱动和多驱动网络。 对于每个单独驱动的网络，分配相应的存储器位置以在运行时存储网络的相应驱动器的值。 对于每个乘法驱动的网络，分配连续的内存块以在运行时存储网络的相应驱动程序的值。 对于混合语言设计，此连续块包含所有涉及的所有HDL语言的驱动程序的值。 生成模拟电路设计的仿真代码。 对于每个单驱动网络，模拟代码被配置为将单驱动网络的相应驱动器的值存储在相应的存储器位置中。 对于每个乘法驱动网络，模拟代码被配置为将相应驱动程序的值存储在指定的存储块中。 生成的模拟代码被存储。

公开(公告)号：US08265918B1

公开(公告)日：2012-09-11

申请号：US12579846

申请日：2009-10-15

申请人： Hem C. Neema ,  Chi Bun Chan ,  Kumar Deepak ,  Nabeel Shirazi

发明人： Hem C. Neema ,  Chi Bun Chan ,  Kumar Deepak ,  Nabeel Shirazi

IPC分类号： G06F17/50

CPC分类号： G06F17/5027 ,  G06F17/5022

摘要： Co-simulation platforms generally include a software-based system and a hardware-based system in which different portions of the circuit design are either simulated in a software-based system or emulated on a hardware-based system. Before a model of circuit design can be co-simulated, the circuit design must be transformed and configured into a form that can execute and interface with a specific hardware-based system. The embodiments of the present invention provide a method, system, and article of manufacture for co-simulation of a portion of a circuit design and achieve an advance in the art by improving co-simulation configuration and setup and providing co-simulation adjustment capabilities during runtime.

摘要翻译： 协同仿真平台通常包括基于软件的系统和基于硬件的系统，其中电路设计的不同部分在基于软件的系统中模拟或在基于硬件的系统上仿真。 在电路设计模型可以共同模拟之前，电路设计必须被转换和配置成可以与特定的基于硬件的系统执行和接口的形式。 本发明的实施例提供了一种用于对电路设计的一部分进行协同仿真的方法，系统和制品，并且通过改进协同仿真配置和设置并提供协同仿真调整能力来实现本领域的进步 运行。

公开(公告)号：US08161436B1

公开(公告)日：2012-04-17

申请号：US12582596

申请日：2009-10-20

申请人： Hem C. Neema

发明人： Hem C. Neema

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： The present invention provides a method, system and article of manufacture for the transformation of parallel blocks into synchronized parallel processes that can be simulated without incurring the overhead of creating extra threads or requiring code modifications in the simulation kernel. This transformation is done in such a way that the parallel behavior is retained in its entirety, and the same simulation time-relative results are produced. The concept of concurrency of processes inherent in HDL languages, including System Verilog, is utilized to achieve the same simulation results via the transformed HDL code, which uses the non-parallel block subset of System Verilog HDL.

摘要翻译： 本发明提供了一种用于将并行块转换为同步并行过程的方法，系统和制品，可以在不产生额外线程或在模拟内核中进行代码修改的开销的情况下进行模拟。 这种转换是以并行行为全部保留的方式完成的，并且产生相同的模拟时间相关结果。 利用HDL语言（包括系统Verilog）固有的进程并发的概念，通过使用System Verilog HDL的非并行块子集的转换HDL代码实现相同的仿真结果。

公开(公告)号：US09117043B1

公开(公告)日：2015-08-25

申请号：US13523799

申请日：2012-06-14

申请人： Lixin Huang ,  Hem C. Neema ,  Sonal Santan

发明人： Lixin Huang ,  Hem C. Neema ,  Sonal Santan

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/5036 ,  G06F17/5045

摘要： Processing a circuit design can include determining a first set of net sensitivity ranges for a net of the circuit design, wherein at least two net sensitivity ranges of the first set are partially overlapping, and translating the first set of net sensitivity ranges into a second set of net sensitivity ranges comprising a plurality of member net sensitivity ranges with no partially overlapping member net sensitivity ranges. A net sensitivity tree can be constructed that includes hierarchically ordered nodes. Each node can specify a net sensitivity range of one member of the second set of net sensitivity ranges.

摘要翻译： 处理电路设计可以包括确定电路设计网的第一组净灵敏度范围，其中第一组的至少两个净灵敏度范围部分重叠，并将第一组净灵敏度范围转换为第二组 的净灵敏度范围包括多个成员净敏感范围，没有部分重叠的成员净敏感度范围。 可以构造包括分层有序节点的净灵敏度树。 每个节点可以指定第二组净灵敏度范围的一个成员的净灵敏度范围。

公开(公告)号：US08868396B1

公开(公告)日：2014-10-21

申请号：US12605077

申请日：2009-10-23

申请人： Nabeel Shirazi ,  L. James Hwang ,  Chi Bun Chan ,  Hem C. Neema ,  Kumar Deepak

发明人： Nabeel Shirazi ,  L. James Hwang ,  Chi Bun Chan ,  Hem C. Neema ,  Kumar Deepak

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method and apparatus for verifying and debugging a circuit design module of a high level programming system is disclosed herein. A circuit design created in a high level programming environment must undergo a number of transformations as it is compiled into a form that can be realized in hardware. At each transformative step, the behavior of the circuit must be verified with a simulation model and debugged if the transformation has changed the behavior of the circuit. The claimed invention presents a novel approach for verifying and debugging between different simulation models and achieves an advance in the art by utilizing the modularized structure of a high-level circuit design to systematically identify simulation mismatches among different simulation models and determine which portions of the circuit design are responsible for the discrepancy.

摘要翻译： 本文公开了一种用于验证和调试高级编程系统的电路设计模块的方法和装置。 在高级编程环境中创建的电路设计必须经过多次转换，因为它被编译成可以在硬件中实现的形式。 在每个变换步骤中，必须用仿真模型验证电路的行为，并且如果转换改变了电路的行为，则进行调试。 所要求保护的发明提出了一种用于在不同仿真模型之间验证和调试的新方法，并通过利用高级电路设计的模块化结构来实现本领域的进步，以系统地识别不同仿真模型之间的模拟不匹配并确定电路的哪些部分 设计负责的差异。

公开(公告)号：US08516413B1

公开(公告)日：2013-08-20

申请号：US13468933

申请日：2012-05-10

申请人： Sandeep S. Deshpande ,  Hem C. Neema ,  Valeria Mihalache ,  Kumar Deepak ,  Sonal Santan ,  David K. Liddell

发明人： Sandeep S. Deshpande ,  Hem C. Neema ,  Valeria Mihalache ,  Kumar Deepak ,  Sonal Santan ,  David K. Liddell

IPC分类号： G06F9/45

CPC分类号： G06F17/5045 ,  G06F17/5022

摘要： One or more embodiments provide a method of HDL simulation that determines dependencies, forcing characteristics, and strength characteristics of nets for the entire circuit design during compilation. Simulation code and data structures are generated for each net, individually, based on the determined characteristics of the respective net. As a result, rather than implementing code for simulation of each net capable of handling every possible combination of the characteristics, less complex code and data structures may be generated for simulation of the nets.

摘要翻译： 一个或多个实施例提供了一种HDL模拟方法，其确定编译期间整个电路设计的网络的依赖性，强制特性和强度特性。 基于相应网的确定的特性，分别为每个网络生成模拟代码和数据结构。 结果，不是为了实现能够处理每个可能的特征组合的每个网络的模拟实现代码，而是可以生成用于模拟网络的较不复杂的代码和数据结构。

公开(公告)号：US08418095B1

公开(公告)日：2013-04-09

申请号：US13468927

申请日：2012-05-10

申请人： Hem C. Neema ,  Sonal Santan ,  Kumar Deepak

发明人： Hem C. Neema ,  Sonal Santan ,  Kumar Deepak

IPC分类号： G06F17/50

CPC分类号： G06F17/5027

摘要： One or more embodiments provide a method of HDL simulation that determines characteristics of nets, such as shorting of nets, non-blocking assignments, etc., for the entire circuit design during compilation. Simulation code and data structures are generated for each net, individually, based on the determined characteristics of the respective net. As a result, rather than implementing code for simulation of each net capable of handling every possible combination of the characteristics, less complex code and data structures may be generated for simulation of the nets.

摘要翻译： 一个或多个实施例提供了HDL模拟的方法，其确定网络的特性，例如在编译期间整个电路设计的网络的短路，非阻塞分配等。 基于相应网的确定的特性，分别为每个网络生成模拟代码和数据结构。 结果，不是为了实现能够处理每个可能的特征组合的每个网络的模拟实现代码，而是可以生成用于模拟网络的较不复杂的代码和数据结构。

公开(公告)号：US08327311B1

公开(公告)日：2012-12-04

申请号：US13188407

申请日：2011-07-21

申请人： Hem C. Neema ,  Sonal Santan ,  Kumar Deepak

发明人： Hem C. Neema ,  Sonal Santan ,  Kumar Deepak

IPC分类号： G06F17/50 ,  G06F11/22

CPC分类号： G06F17/5022 ,  G06F2217/84

摘要： Approaches for generating functions for activating processes in a simulation model. At least two mutually exclusive sub-ranges of a plurality of bits of a net of the circuit design are determined. A respective process set associated with each sub-range of the plurality of bits is determined. The specification of a wakeup function includes for each sub-range of the plurality of bits, a test for a change in value of at least one bit in the sub-range of the plurality of bits, and an initiation of each process in the associated process set in response to a detected change in value of the at least one bit. The specification also includes control, responsive to a detected change in value of at least one bit in one of the sub-ranges, that bypasses a test for a change in value of at least one bit in at least one other of the sub-ranges.

摘要翻译： 在仿真模型中生成激活过程的功能的方法。 确定电路设计网的多个位的至少两个相互排斥的子范围。 确定与多个位的每个子范围相关联的相应处理集。 唤醒功能的规范包括对于多个比特的每个子范围，对多个比特的子范围中的至少一个比特的值的变化的测试以及相关联的每个进程的启动 响应于检测到的至少一个位的值的改变而设置的处理。 该规范还包括响应于子范围中的一个子范围中检测到的至少一个比特的值的改变的控制，其绕过用于子范围中的至少另一个中的至少一个比特的值的改变的测试 。

公开(公告)号：US08074077B1

公开(公告)日：2011-12-06

申请号：US11786954

申请日：2007-04-12

申请人： Hem C. Neema ,  Kumar Deepak ,  Jimmy Zhenming Wang

发明人： Hem C. Neema ,  Kumar Deepak ,  Jimmy Zhenming Wang

IPC分类号： G06F12/14

CPC分类号： G06F21/6227

摘要： A method of securing a circuit design can include generating a string including a plurality of elements. The plurality of elements can include elements of design information selected from within the circuit design and at least one security element indicating whether the circuit design is protected. The method further can include permuting the plurality of elements of the string, encrypting the permuted string using a key shared with a circuit design tool, and including the permuted and encrypted string within the circuit design.

摘要翻译： 确保电路设计的方法可以包括生成包括多个元件的串。 多个元件可以包括从电路设计中选择的设计信息的元件和指示电路设计是否被保护的至少一个安全元件。 该方法还可以包括对字符串的多个元素进行置换，使用与电路设计工具共享的密钥来加密置换的字符串，并且在电路设计中包括置换和加密的字符串。

公开(公告)号：US07721090B1

公开(公告)日：2010-05-18

申请号：US11370116

申请日：2006-03-07

申请人： Kumar Deepak ,  Satish R. Ganesan ,  Jimmy Zhenming Wang ,  Sundararajarao Mohan ,  Ralph D. Wittig ,  Hem C. Neema

发明人： Kumar Deepak ,  Satish R. Ganesan ,  Jimmy Zhenming Wang ,  Sundararajarao Mohan ,  Ralph D. Wittig ,  Hem C. Neema

IPC分类号： H04L29/06 ,  G06F21/00 ,  G06F12/14 ,  G06F17/50

CPC分类号： G06F21/12 ,  G06F17/5022 ,  G06F21/10 ,  G06F21/76 ,  G06F2217/66

摘要： A method of creating a secure intellectual property (IP) representation of a circuit design for use with a software-based simulator can include translating a hardware description language representation of the circuit design into an encrypted intermediate form and compiling the intermediate form of the circuit design to produce encrypted object code. The method further can include linking the encrypted object code with a simulation kernel library thereby creating the secure IP representation of the circuit design. The secure IP can include an encrypted simulation model of the circuit design and a simulation kernel configured to execute the encrypted simulation model.

摘要翻译： 创建用于与基于软件的模拟器一起使用的电路设计的安全知识产权（IP）表示的方法可以包括将电路设计的硬件描述语言表示转换为加密的中间形式并编译电路设计的中间形式 以产生加密的对象代码。 该方法还可以包括将加密的对象代码与仿真内核库链接，从而创建电路设计的安全IP表示。 安全IP可以包括电路设计的加密仿真模型和被配置为执行加密仿真模型的仿真内核。