公开(公告)号：US07669017B1

公开(公告)日：2010-02-23

申请号：US11527802

申请日：2006-09-27

申请人： Hemang Maheshkumar Parekh ,  Hai-Jo Tarn ,  Gabor Szedo ,  Vanessa Yu-Mei Chou ,  Jeffrey Allan Graham ,  Elizabeth R. Cowie

发明人： Hemang Maheshkumar Parekh ,  Hai-Jo Tarn ,  Gabor Szedo ,  Vanessa Yu-Mei Chou ,  Jeffrey Allan Graham ,  Elizabeth R. Cowie

IPC分类号： G06F12/00

CPC分类号： H04L27/263 ,  G06F5/16 ,  G06F17/142

摘要： A method of buffering data in a circuit processing data in both a natural address order and a modified address order is described. The method comprises the steps of storing a first block of data according to a first addressing order of a natural address order or a modified address order; reading the first block of data stored in a buffer according to the other addressing order of the natural address order and the modified address order; and simultaneously writing a second block of data to the buffer in the other addressing order while reading the first block of data stored in a buffer according to the other addressing order.

摘要翻译： 描述了以自然地址顺序和修改的地址顺序在电路处理数据中缓冲数据的方法。 该方法包括以下步骤：根据自然地址顺序或修改的地址顺序的第一寻址顺序存储第一数据块; 根据自然地址顺序和修改的地址顺序的另一寻址顺序读取存储在缓冲器中的第一数据块; 并且在按照另一个寻址顺序读取存储在缓冲器中的第一数据块时，以另一寻址顺序同时将第二数据块写入缓冲器。

公开(公告)号：US07793200B1

公开(公告)日：2010-09-07

申请号：US11527830

申请日：2006-09-27

申请人： Hemang Maheshkumar Parekh ,  Elizabeth R. Cowie ,  Jeffrey Allan Graham ,  Hai-Jo Tarn ,  Vanessa Yi-Mei Chou

发明人： Hemang Maheshkumar Parekh ,  Elizabeth R. Cowie ,  Jeffrey Allan Graham ,  Hai-Jo Tarn ,  Vanessa Yi-Mei Chou

IPC分类号： H03M13/03

CPC分类号： H03M13/4169 ,  H03M13/4176 ,  H03M13/6505 ,  H03M13/6566

摘要： A method of accessing a memory of a trellis decoder. The method comprises the steps of writing a first block of data associated with a trellis function to a first memory block; writing a second block of data associated with the trellis function to a second memory block; simultaneously writing a third block of data to a third memory block and reading the second block of data from the second memory block to generate training data; and simultaneously reading data to be decoded from the first memory block and writing a fourth block of data to the first memory block and generating training data associated with the third block of data. A circuit for accessing a memory of a trellis decoder is also described.

摘要翻译： 访问网格解码器的存储器的方法。 该方法包括将与网格功能相关联的第一数据块写入第一存储器块的步骤; 将与网格功能相关联的第二数据块写入第二存储器块; 同时将第三块数据写入第三存储器块，并从第二存储器块读取第二数据块以产生训练数据; 同时从第一存储块读取要解码的数据，并向第一存储块写入第四数据块，并生成与第三数据块相关联的训练数据。 还描述了用于访问网格解码器的存储器的电路。

公开(公告)号：US07610453B1

公开(公告)日：2009-10-27

申请号：US11527883

申请日：2006-09-27

申请人： Hemang Maheshkumar Parekh ,  Jeffrey Allan Graham ,  Hai-Jo Tarn ,  Elizabeth R. Cowie ,  Vanessa Yi-Mei Chou

发明人： Hemang Maheshkumar Parekh ,  Jeffrey Allan Graham ,  Hai-Jo Tarn ,  Elizabeth R. Cowie ,  Vanessa Yi-Mei Chou

IPC分类号： G06F12/00

CPC分类号： G06F7/785

摘要： Each array in a sequence of arrays is reordered. A first port receives in a first serial order a number of values in each array in the sequence and a second port transmits the values in a different second serial order. For each value in each array in the sequence, the address generator generates an address within a range of zero through one less than the number of values in the array. For each address from the generator, the memory performs an access to a location corresponding to the address in the memory. The access for each address includes a read from the location before a write to the location. For each array in the sequence, the writes for the addresses serially write the values of the array in the first serial order and the reads for the addresses serially read the values in the second serial order.

摘要翻译： 一系列数组中的每个数组被重新排序。 第一端口以第一串行顺序接收序列中每个阵列中的多个值，并且第二端口以不同的第二串行顺序发送值。 对于序列中每个数组中的每个值，地址生成器将生成一个范围从零到小于数组中数值的地址。 对于来自发生器的每个地址，存储器执行对与存储器中的地址相对应的位置的访问。 每个地址的访问包括从写入位置之前的位置读取。 对于序列中的每个数组，地址的写入以第一个串行顺序串行写入数组的值，并且地址的读取以串行顺序读取第二个串行顺序的值。