公开(公告)号：US06803640B1

公开(公告)日：2004-10-12

申请号：US09633366

申请日：2000-08-07

申请人： In-Jung Lee ,  Heon-Joung Shin

发明人： In-Jung Lee ,  Heon-Joung Shin

IPC分类号： H01L2708

CPC分类号： H01L25/16 ,  H01L27/0805 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a WACC and a fabricating method thereof to prevent the occurrence of lifting between a polysilicon layer pattern and blocking metal layer of an upper electrode. In order to accomplish the object of the present invention, there is provided a capacitor having upper and lower electrodes and a dielectric layer therebetween, wherein the upper electrode has a polysilicon pattern constructed in a deposition structure of “first undoped polysilicon layer/doped polysilicon layer/second undoped polysilicon layer” to be connected with a first metal pattern at the top portion, and the lower electrode has first and second metal patterns to be connected with a p++ type silicon substrate at the bottom portion. The first metal pattern is preferably constructed in a deposition structure of “blocking metal layer/aluminum layer”, where the blocking metal layer is preferably constructed in a “Ti/TiN” deposition structure. Accordingly, the capacitor is constructed to enable the blocking metal layer to be in contact with an undoped polysilicon layer, rather than a doped polysilicon layer as in conventional embodiments, to achieve an effect that the doffing level of the polysilicon layer is reduced as compared to the conventional configuration, thereby enhancing formation of the silicide layer between the polysilicon layer and the blocking metal layer to improve adhesion and prevent the occurrence of lifting.

摘要翻译： 本发明涉及一种WACC及其制造方法，用于防止在多晶硅层图案和上电极的阻挡金属层之间产生升高。 为了实现本发明的目的，提供一种电容器，其具有上电极和下电极以及介电层之间，其中上电极具有以“第一未掺杂多晶硅层/掺杂多晶硅层”的沉积结构构成的多晶硅图案 /第二未掺杂多晶硅层“，以在顶部与第一金属图案连接，下电极具有在底部与p ++型硅基板连接的第一和第二金属图案。 第一金属图案优选构造为“阻挡金属层/铝层”的沉积结构，其中阻挡金属层优选构造在“Ti / TiN”沉积结构中。 因此，电容器被构造成使得阻挡金属层能够与未掺杂多晶硅层接触，而不是如常规实施例中的掺杂多晶硅层，以实现多晶硅层的落纱电平降低的效果， 从而增强多晶硅层和阻挡金属层之间的硅化物层的形成，从而提高粘附性并防止提升的发生。