公开(公告)号：US06803640B1

公开(公告)日：2004-10-12

申请号：US09633366

申请日：2000-08-07

申请人： In-Jung Lee ,  Heon-Joung Shin

发明人： In-Jung Lee ,  Heon-Joung Shin

IPC分类号： H01L2708

CPC分类号： H01L25/16 ,  H01L27/0805 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a WACC and a fabricating method thereof to prevent the occurrence of lifting between a polysilicon layer pattern and blocking metal layer of an upper electrode. In order to accomplish the object of the present invention, there is provided a capacitor having upper and lower electrodes and a dielectric layer therebetween, wherein the upper electrode has a polysilicon pattern constructed in a deposition structure of “first undoped polysilicon layer/doped polysilicon layer/second undoped polysilicon layer” to be connected with a first metal pattern at the top portion, and the lower electrode has first and second metal patterns to be connected with a p++ type silicon substrate at the bottom portion. The first metal pattern is preferably constructed in a deposition structure of “blocking metal layer/aluminum layer”, where the blocking metal layer is preferably constructed in a “Ti/TiN” deposition structure. Accordingly, the capacitor is constructed to enable the blocking metal layer to be in contact with an undoped polysilicon layer, rather than a doped polysilicon layer as in conventional embodiments, to achieve an effect that the doffing level of the polysilicon layer is reduced as compared to the conventional configuration, thereby enhancing formation of the silicide layer between the polysilicon layer and the blocking metal layer to improve adhesion and prevent the occurrence of lifting.

摘要翻译： 本发明涉及一种WACC及其制造方法，用于防止在多晶硅层图案和上电极的阻挡金属层之间产生升高。 为了实现本发明的目的，提供一种电容器，其具有上电极和下电极以及介电层之间，其中上电极具有以“第一未掺杂多晶硅层/掺杂多晶硅层”的沉积结构构成的多晶硅图案 /第二未掺杂多晶硅层“，以在顶部与第一金属图案连接，下电极具有在底部与p ++型硅基板连接的第一和第二金属图案。 第一金属图案优选构造为“阻挡金属层/铝层”的沉积结构，其中阻挡金属层优选构造在“Ti / TiN”沉积结构中。 因此，电容器被构造成使得阻挡金属层能够与未掺杂多晶硅层接触，而不是如常规实施例中的掺杂多晶硅层，以实现多晶硅层的落纱电平降低的效果， 从而增强多晶硅层和阻挡金属层之间的硅化物层的形成，从而提高粘附性并防止提升的发生。

公开(公告)号：US06703656B2

公开(公告)日：2004-03-09

申请号：US09917844

申请日：2001-07-26

申请人： Brent Keeth ,  Pierre C. Fazan

发明人： Brent Keeth ,  Pierre C. Fazan

IPC分类号： H01L2708

CPC分类号： H01L27/105 ,  H01L27/108 ,  H01L27/10811 ,  Y10T29/49121

摘要： Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. In accordance with aspects of the invention, considerably greater numbers of die sites per wafer are achieved for 6-inch, 8-inch and 12-inch wafers for 4M, 16M, 64M and 256M integration levels. Further, a semiconductor memory device includes i) a plurality of functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells, at least one of the memory arrays containing at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells.

摘要翻译： 公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。 根据本发明的方面，对于用于4M，16M，64M和256M积分级别的6英寸，8英寸和12英寸晶片，实现了相当大数量的每个晶片的晶片位置。 此外，半导体存储器件包括：i）布置在形成在半导体管芯上的多个存储器阵列中的多个功能和可操作地寻址的存储器单元; 以及ii）形成在所述半导体管芯上的电路，允许将数据写入到所述存储器单元中的一个或多个存储单元并从其读取，所述存储器阵列中的至少一个包含至少100平方微米的连续管芯表面区域，其具有至少170个 功能和可操作地寻址的存储单元。

公开(公告)号：US06696721B2

公开(公告)日：2004-02-24

申请号：US10376260

申请日：2003-03-03

申请人： Katsuhiko Hieda

发明人： Katsuhiko Hieda

IPC分类号： H01L2708

CPC分类号： H01L27/11502 ,  H01L27/10855 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/90 ,  H01L28/91

摘要： A plurality of storage node electrodes are formed on a semiconductor substrate. A capacitor insulating film is formed on the storage node electrodes. A plate electrode, facing the storage node electrodes, is formed on the capacitor insulating film. A cavity is formed in the plate electrode.

摘要翻译： 多个存储节点电极形成在半导体衬底上。 在存储节点电极上形成电容绝缘膜。 在电容器绝缘膜上形成面向存储节点电极的平板电极。 在平板电极中形成空腔。

公开(公告)号：US06674113B2

公开(公告)日：2004-01-06

申请号：US10254692

申请日：2002-09-25

申请人： Matthias Goldbach ,  Thomas Hecht ,  Jörn Lützen ,  Bernhard Sell

发明人： Matthias Goldbach ,  Thomas Hecht ,  Jörn Lützen ,  Bernhard Sell

IPC分类号： H01L2708

CPC分类号： H01L27/10861

摘要： A trench capacitor has a first capacitor electrode, a second capacitor electrode, and a dielectric, which is arranged between the capacitor electrodes. The first capacitor electrode has a tube-like structure, which extends into a substrate. The second capacitor electrode includes a first section which is opposite to the internal side of the tube-like structure, with the dielectric arranged therebetween, and a second section, which is opposite to the external side of the tube-like structure with the dielectric arranged therebetween.

摘要翻译： 沟槽电容器具有布置在电容器电极之间的第一电容器电极，第二电容器电极和电介质。 第一电容器电极具有延伸到基板中的管状结构。 第二电容器电极包括与管状结构的内侧相对的第一部分，其间布置有电介质，第二部分与管状结构的外侧相反，电介质布置 之间。

公开(公告)号：US06646299B2

公开(公告)日：2003-11-11

申请号：US10126365

申请日：2002-04-19

申请人： Josef Willer ,  Christofer Hierold

发明人： Josef Willer ,  Christofer Hierold

IPC分类号： H01L2708

CPC分类号： H01L28/92 ,  H01L28/55

摘要： A first capacitor electrode and at least part of a second capacitor electrode of a capacitor are produced in depressions of an auxiliary layer by electroplating. The auxiliary layer is then removed and at least partially replaced by a capacitor dielectric. The first capacitor electrode and the part of the second capacitor electrode may be composed of a metal, for example platinum. The capacitor dielectric can be composed, for example, of barium-strontium-titanate.

公开(公告)号：US06734489B2

公开(公告)日：2004-05-11

申请号：US10122387

申请日：2002-04-16

申请人： Noboru Morimoto ,  Kinya Goto ,  Masahiro Matsumoto

发明人： Noboru Morimoto ,  Kinya Goto ,  Masahiro Matsumoto

IPC分类号： H01L2708

CPC分类号： H01L23/5223 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76838 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： A second-level wire is formed by a dual damascene process in a insulating film. In an upper surface of the first insulating film a metal film is formed and serves as a first electrode of an MIM-type capacitor. A second insulating films has a structure in which a plurality of insulating films are layered on a second interconnection layer, in this order. In a first insulating film of the plurality of insulating films, a second electrode of the MIM-type capacitor is formed. The second electrode has a first metal film formed on a second insulating film of the plurality of the insulating films and a second metal film is formed on the first metal film. A portion of the second insulating film which is sandwiched between the first electrode and the second electrode of the MIM-type capacitor serves as a capacitor dielectric film of the MIM-type capacitor. In the second insulating film, a third-level wire is formed Thus, a semiconductor device and a method of manufacturing the same are provided such that the MIM-type capacitor is formed together with metal wires with no additional complicated step.

摘要翻译： 二级线由绝缘膜中的双镶嵌工艺形成。 在第一绝缘膜的上表面形成有金属膜，作为MIM型电容器的第一电极。 第二绝缘膜具有这样的结构，其中多个绝缘膜依次层叠在第二互连层上。 在多个绝缘膜的第一绝缘膜中形成MIM型电容器的第二电极。 第二电极具有形成在多个绝缘膜的第二绝缘膜上的第一金属膜，并且在第一金属膜上形成第二金属膜。 夹在MIM型电容器的第一电极和第二电极之间的第二绝缘膜的一部分用作MIM型电容器的电容器电介质膜。 在第二绝缘膜中，形成第三级线。因此，提供半导体器件及其制造方法，使得MIM型电容器与金属线一起形成，而不需要额外的复杂步骤。

公开(公告)号：US06649964B2

公开(公告)日：2003-11-18

申请号：US09860635

申请日：2001-05-21

申请人： Young-Hoon Kim

发明人： Young-Hoon Kim

IPC分类号： H01L2708

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： The semiconductor substrate body-substrate contact structure for a SOI device includes an SOI substrate having a semiconductor substrate, a buried insulating film formed on an upper surface of the semiconductor substrate, and a semiconductor body layer formed on an upper surface of the buried insulating film. The SOI substrate includes a trench exposing an upper surface of the semiconductor substrate, and semiconductive side wall spacers are formed on side walls of the trench. A device isolation insulating film is formed in the trench.

公开(公告)号：US06642566B1

公开(公告)日：2003-11-04

申请号：US10195601

申请日：2002-06-28

申请人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Haining Yang

发明人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Haining Yang

IPC分类号： H01L2708

CPC分类号： H01L27/10876 ,  H01L27/10864 ,  H01L27/10888 ,  H01L27/10891

摘要： A DRAM array having a DRAM cell employing vertical transistors increases electrical reliability and reduces bitline capacitance by use of an asymmetric structure in the connection between the wordline and the transistor, thereby permitting the use of a wider connection between the wordline and the transistor electrode and using the wordline as an etch stop to protect the transistor gate during the patterning of the wordlines.

摘要翻译： 具有使用垂直晶体管的DRAM单元的DRAM阵列通过在字线和晶体管之间的连接中使用不对称结构来增加电可靠性并降低位线电容，从而允许在字线和晶体管电极之间使用更宽的连接并且使用 该字线作为蚀刻停止以在图形化字线期间保护晶体管栅极。

公开(公告)号：US06621113B2

公开(公告)日：2003-09-16

申请号：US10122585

申请日：2002-04-15

申请人： Chiu-Te Lee

发明人： Chiu-Te Lee

IPC分类号： H01L2708

CPC分类号： H01L27/10861 ,  H01L21/76232

摘要： A method of fabricating a self-aligned shallow trench isolation. A mask layer, two deep trenches and two internal electrodes of a capacitor are sequentially formed on a substrate. Two conductive layers are used to completely fill the two deep trenches. Then, two spacers are formed on exposed sides of the two conductive layers, and two doped regions are formed in a portion of the substrate located next to the two conductive layers. A patterned photoresist layer is formed to expose at least the spacers located in between the two deep trenches and the mask layer. The photoresist layer and the spacers are utilized as masks to etch away the exposed mask layer. The photoresist layer is utilized again as a mask to etch the exposed spacers and a portion of the exposed substrate. Sequentially, a remained portion of the photoresist layer and a portion of the conductive layers are removed. A remained mask layer is used as a mask to remove a portion of the exposed substrate, and a trench is thus formed. Finally, a shallow trench isolation is formed in the trench.

摘要翻译： 一种制造自对准浅沟槽隔离的方法。 在基板上依次形成掩模层，电容器的两个深沟槽和两个内部电极。 两个导电层用于完全填充两个深沟槽。 然后，在两个导电层的暴露侧上形成两个间隔物，并且在位于两个导电层旁边的衬底的一部分中形成两个掺杂区域。 形成图案化的光致抗蚀剂层以至少露出位于两个深沟槽和掩模层之间的间隔物。 光致抗蚀剂层和间隔物用作掩模以蚀刻掉暴露的掩模层。 光致抗蚀剂层再次用作掩模以蚀刻暴露的间隔物和暴露的基底的一部分。 接着，去除光致抗蚀剂层的剩余部分和导电层的一部分。 使用保留的掩模层作为掩模以去除暴露的衬底的一部分，从而形成沟槽。 最后，在沟槽中形成浅沟槽隔离。

公开(公告)号：US06573549B1

公开(公告)日：2003-06-03

申请号：US10177773

申请日：2002-06-21

申请人： Xiaowei Deng ,  Theodore W. Houston

发明人： Xiaowei Deng ,  Theodore W. Houston

IPC分类号： H01L2708

CPC分类号： H01L27/12 ,  H01L27/1108

摘要： An embodiment of the instant invention is a memory device comprising: a memory cell including: a first transistor (108 of FIG. 1) having a control electrode, a current path, and a backgate/body connection electrically connected to the control electrode of the first transistor; and a second transistor (130 of FIG. 1) having a control electrode, a current path, and a backgate/body connection electrically connected to the control electrode of the second transistor and the current path of the first transistor, the current path of the second transistor connected to the backgate/body connection of the first transistor; an input/output conductor; and a pass transistor coupling the memory cell to the input/output conductor.

摘要翻译： 本发明的实施例是一种存储器件，包括：存储单元，包括：第一晶体管（图1的108），其具有控制电极，电流路径和电连接到 第一晶体管; 和具有电连接到第二晶体管的控制电极和第一晶体管的电流通路的控制电极，电流路径和背栅极/主体连接的第二晶体管（130），第一晶体管的电流通路 第二晶体管连接到第一晶体管的背栅极/主体连接; 输入/输出导体; 以及将存储单元耦合到输入/输出导体的传输晶体管。