公开(公告)号：US5851873A

公开(公告)日：1998-12-22

申请号：US734602

申请日：1996-10-22

申请人： Ichiro Murai ,  Hidemi Arakawa ,  Shinobu Shigeta

发明人： Ichiro Murai ,  Hidemi Arakawa ,  Shinobu Shigeta

IPC分类号： H01L21/336 ,  H01L21/265 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10852

摘要： A semiconductor memory device has a long refresh time and offers high reliability by minimizing junction leakage current, resulting in increased charge retention time. This is achieved by optimizing the diffusion layer junction depth formed in a deeper region of the semiconductor substrate which is in electrical contact with the impurity diffusion layer. Typically, junction depth is in excess of 0.1 .mu.m. Two methods for achieving such a structure are also provided. In one method, implantation voltage in excess of 80 KeV is used to implant P ions to form a high carrier concentration profile at a junction depth of greater than 0.1 .mu.m. In another method, implantation process are carried out in two steps so as to force the previously implanted ions deeper into the storage node electrode, and a subsequent heat treatment is carried out to further distribute the dopant ions into the substrate of the semiconductor substrate so as to disperse crystal defects into the substrate. The resulting structure is essentially free of crystal defects which cause current leakage from the boundary region between the dopant diffusion layer and the substrate in the conventional memory cell structure.

摘要翻译： 半导体存储器件具有较长的刷新时间，并且通过最小化结漏电流提供高可靠性，导致增加的电荷保留时间。 这通过优化在与杂质扩散层电接触的半导体衬底的较深区域中形成的扩散层结深而实现。 通常，结深度超过0.1μm。 还提供了用于实现这种结构的两种方法。 在一种方法中，使用超过80keV的注入电压来注入P离子，以在大于0.1μm的结深处形成高载流子浓度分布。 在另一种方法中，以两个步骤进行注入工艺，以便将先前注入的离子强制进入存储节点电极中，并进行随后的热处理，以进一步将掺杂剂离子分布到半导体衬底的衬底中，以便 以将晶体缺陷分散到衬底中。 所得到的结构基本上没有晶体缺陷，这些缺陷在常规的存储单元结构中引起了掺杂剂扩散层和衬底之间的边界区域的电流泄漏。

公开(公告)号：US6087213A

公开(公告)日：2000-07-11

申请号：US094663

申请日：1998-06-15

申请人： Ichiro Murai ,  Hidemi Arakawa ,  Shinobu Shigeta

发明人： Ichiro Murai ,  Hidemi Arakawa ,  Shinobu Shigeta

IPC分类号： H01L21/336 ,  H01L21/265 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L27/10852

摘要： A method of making a semiconductor memory device is discussed, which has a long refresh time and offers high reliability by minimizing junction leakage current, resulting in increased charge retention time. This is achieved by optimizing the diffusion layer junction depth formed in a deeper region of the semiconductor substrate which is in electrical contact with the impurity diffusion layer. Typically, junction depth is in excess of 0.1 .mu.m. Two methods for achieving such a structure are also provided. In one method, implantation voltage in excess of 80 KeV is used to implant P ions to form a high carrier concentration profile at a junction depth of greater than 0.1 .mu.m. In another method, implantation process are carried out in two steps so as to force the previously implanted ions deeper into the storage node electrode, and a subsequent heat treatment is carried out to further distribute the dopant ions into the substrate of the semiconductor substrate so as to disperse crystal defects into the substrate. The resulting structure is essentially free of crystal defects which cause current leakage from the boundary region between the dopant diffusion layer and the substrate in the conventional memory cell structure.

摘要翻译： 讨论了制造半导体存储器件的方法，其具有长的刷新时间，并且通过最小化结漏电流提供高可靠性，导致增加的电荷保持时间。 这通过优化在与杂质扩散层电接触的半导体衬底的较深区域中形成的扩散层结深而实现。 通常，结深度超过0.1μm。 还提供了用于实现这种结构的两种方法。 在一种方法中，使用超过80keV的注入电压来注入P离子，以在大于0.1μm的结深处形成高载流子浓度分布。 在另一种方法中，以两个步骤进行注入工艺，以便将先前注入的离子强制进入存储节点电极中，并进行随后的热处理，以进一步将掺杂剂离子分布到半导体衬底的衬底中，以便 以将晶体缺陷分散到衬底中。 所得到的结构基本上没有晶体缺陷，这些缺陷在常规的存储单元结构中引起了掺杂剂扩散层和衬底之间的边界区域的电流泄漏。