公开(公告)号：US07504850B2

公开(公告)日：2009-03-17

申请号：US11499498

申请日：2006-08-03

申请人： Satoshi Kuboyama ,  Hiroyuki Shindou ,  Yoshiya Iide ,  Akiko Makihara

发明人： Satoshi Kuboyama ,  Hiroyuki Shindou ,  Yoshiya Iide ,  Akiko Makihara

IPC分类号： H03K19/003

CPC分类号： H03K19/00338

摘要： Disclosed is an inverter, a NAND element, a NOR element, a memory element and a data latch circuit which exhibit high tolerance to single event effect (SEE). In an SEE tolerant inverter (3I), each of a p-channel MOS transistor and a n-channel MOS transistor which form an inverter is connected in series with an additional second transistor of the same conductive type as that thereof so as to form a double structure (3P1, 3P2; 3N1, 3N2). Further, a node A between the two p-channel MOS transistors and a node (B) between the two n-channel MOS transistors are connected together through a connection line. Each of an SEE tolerant memory element and an SEE tolerant data latch circuit comprises this SEE tolerant inverter (3I).

摘要翻译： 公开了对单一事件效应（SEE）表现出高容忍度的反相器，NAND元件，NOR元件，存储元件和数据锁存电路。 在SEE容限逆变器（3I）中，形成反相器的p沟道MOS晶体管和n沟道MOS晶体管中的每一个与与其相同的导电类型的附加的第二晶体管串联连接，以形成 双重结构（3P1,3P2; 3N1,3N2）。 此外，两个p沟道MOS晶体管之间的节点A和两个n沟道MOS晶体管之间的节点（B）通过连接线连接在一起。 每个SEE容限存储器元件和SEE容限数据锁存电路包括该SEE容限逆变器（3I）。

公开(公告)号：US07576583B2

公开(公告)日：2009-08-18

申请号：US11638189

申请日：2006-12-12

申请人： Satoshi Kuboyama ,  Hiroyuki Shindou ,  Yoshiya Ilde ,  Akiko Makihara

发明人： Satoshi Kuboyama ,  Hiroyuki Shindou ,  Yoshiya Ilde ,  Akiko Makihara

IPC分类号： H03K3/00

CPC分类号： H03K3/0375

摘要： Disclosed are a latch circuit and a flip-flop circuit, which are capable of suppressing occurrence of a single-event effect, and, in the event of a single-event transient (SET), elimination adverse effects thereof on the circuit. The latch circuit comprises a dual-port inverter, and a dual-port clocked inverter including no transmission gate to reduce a region of strong electric field to be formed. A delay time is set up in a clock to eliminate adverse effects of the SET, and a leading-edge delayed clock to be entered into one of two storage nodes is generated in such a manner as to delay a transition of the storage node and the entire storage nodes from a latch mode to a through mode while preventing an increase in hold time due to the delay time.

摘要翻译： 公开了一种锁存电路和触发器电路，其能够抑制单事件效应的发生，并且在单事件瞬变（SET）的情况下，消除对电路的不利影响。 锁存电路包括双端口反相器和双端口时钟反相器，其不包括传输门，以减少要形成的强电场区域。 延迟时间设置在时钟中以消除SET的不利影响，并且以这样的方式生成要输入到两个存储节点之一的前沿延迟时钟，以延迟存储节点和 整个存储节点从锁存模式到直通模式，同时防止由于延迟时间引起的保持时间的增加。

公开(公告)号：US20070132496A1

公开(公告)日：2007-06-14

申请号：US11638189

申请日：2006-12-12

申请人： Satoshi Kuboyama ,  Hiroyuki Shindou ,  Yoshiya Ilde ,  Akiko Makihara

发明人： Satoshi Kuboyama ,  Hiroyuki Shindou ,  Yoshiya Ilde ,  Akiko Makihara

IPC分类号： H03K3/00

CPC分类号： H03K3/0375

摘要： Disclosed are a latch circuit and a flip-flop circuit, which are capable of suppressing occurrence of a single-event effect, and, in the event of a single-event transient (SET), elimination adverse effects thereof on the circuit. The latch circuit comprises a dual-port inverter, and a dual-port clocked inverter including no transmission gate to reduce a region of strong electric field to be formed. A delay time is set up in a clock to eliminate adverse effects of the SET, and a leading-edge delayed clock to be entered into one of two storage nodes is generated in such a manner as to delay a transition of the storage node and the entire storage nodes from a latch mode to a through mode while preventing an increase in hold time due to the delay time.

摘要翻译： 公开了一种锁存电路和触发器电路，其能够抑制单事件效应的发生，并且在单事件瞬变（SET）的情况下，消除对电路的不利影响。 锁存电路包括双端口反相器和双端口时钟反相器，其不包括传输门，以减少要形成的强电场区域。 延迟时间设置在时钟中以消除SET的不利影响，并且以这样的方式生成要输入到两个存储节点之一的前沿延迟时钟，以延迟存储节点和 整个存储节点从锁存模式到直通模式，同时防止由于延迟时间引起的保持时间的增加。

公开(公告)号：US20070069305A1

公开(公告)日：2007-03-29

申请号：US11499498

申请日：2006-08-03

申请人： Satoshi Kuboyama ,  Hiroyuki Shindou ,  Yoshiya Iide ,  Akiko Makihara

发明人： Satoshi Kuboyama ,  Hiroyuki Shindou ,  Yoshiya Iide ,  Akiko Makihara

IPC分类号： H01L29/94

CPC分类号： H03K19/00338

摘要： Disclosed is an inverter, a NAND element, a NOR element, a memory element and a data latch circuit which exhibit high tolerance to single event effect (SEE). In an SEE tolerant inverter (3I), each of a p-channel MOS transistor and a n-channel MOS transistor which form an inverter is connected in series with an additional second transistor of the same conductive type as that thereof so as to form a double structure (3P1, 3P2; 3N1, 3N2). Further, a node A between the two p-channel MOS transistors and a node (B) between the two n-channel MOS transistors are connected together through a connection line. Each of an SEE tolerant memory element and an SEE tolerant data latch circuit comprises this SEE tolerant inverter (3I).

摘要翻译： 公开了对单一事件效应（SEE）表现出高容忍度的反相器，NAND元件，NOR元件，存储元件和数据锁存电路。 在SEE容限逆变器（3I）中，形成反相器的p沟道MOS晶体管和n沟道MOS晶体管中的每一个与与其相同导电类型的另外的第二晶体管串联连接，以形成 双重结构（3 P 1,3 P 2; 3 N 1,3 N 2）。 此外，两个p沟道MOS晶体管之间的节点A和两个n沟道MOS晶体管之间的节点（B）通过连接线连接在一起。 每个SEE容限存储器元件和SEE容限数据锁存电路包括该SEE容限逆变器（3I）。