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    Logic verification system
    2.
    发明申请
    Logic verification system 审中-公开
    逻辑验证系统

    公开(公告)号：US20080306722A1

    公开(公告)日：2008-12-11

    申请号：US12068628

    申请日：2008-02-08

    申请人： Mototsugu Fujii ,  Osamu Tada ,  Kazunobu Morimoto ,  Akira Yamagiwa ,  Hisashi Nanao

    发明人： Mototsugu Fujii ,  Osamu Tada ,  Kazunobu Morimoto ,  Akira Yamagiwa ,  Hisashi Nanao

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5027

    摘要： There is provided a logic verification system having improved development time and design quality, in which all pins of an FPGA module are wired in direct between the FPGA module and a bridge circuit used in the verification processes of a logic simulator accelerator and a logic emulator, a cutting end of the verification object logic is assigned to an external interface connector of the FPGA module when the logic simulation is accelerated, and the correspondence between each pin of external interface connector of the FPGA module and logic signal is performed on the logic simulator on the general purpose processor.

    摘要翻译： 提供了具有改进的开发时间和设计质量的逻辑验证系统，其中FPGA模块的所有引脚直接连接在FPGA模块和用于逻辑模拟器加速器和逻辑仿真器的验证过程中的桥接电路之间， 当逻辑模拟被加速时，验证对象逻辑的切割端被分配给FPGA模块的外部接口连接器，并且在逻辑模拟器上执行FPGA模块的外部接口连接器的每个引脚与逻辑信号之间的对应关系 通用处理器。

    Broadcast system in disk array controller
    3.
    发明授权
    Broadcast system in disk array controller 失效
    磁盘阵列控制器中的广播系统

    公开(公告)号：US06658529B2

    公开(公告)日：2003-12-02

    申请号：US10098519

    申请日：2002-03-18

    申请人： Akira Fujibayashi ,  Atsushi Tanaka ,  Nobuyuki Minowa ,  Hikari Mikami ,  Hisashi Nanao

    发明人： Akira Fujibayashi ,  Atsushi Tanaka ,  Nobuyuki Minowa ,  Hikari Mikami ,  Hisashi Nanao

    IPC分类号： G06F1200

    CPC分类号： G06F3/0613 ,  G06F3/0658 ,  G06F3/0683

    摘要： A disk controller which includes a plurality of interfaces to host computers or disk devices, each interface having a processor, a memory unit coupled to the interfaces in a one-to-one ratio by respective access paths, the memory unit having a memory in which information is stored, and a common bus coupling to the processors included in the interfaces. Each processor of each interface transmits broadcast data to all of the processors of the interfaces, except its own, by way of the common bus.

    摘要翻译： 一种磁盘控制器，其包括多个接口以主机计算机或磁盘设备，每个接口具有处理器，存储单元以相对于所述接口的一对一比例耦合到所述接口，所述存储器单元具有存储器， 存储信息，以及耦合到接口中包括的处理器的公共总线。 每个接口的每个处理器通过公共总线将广播数据发送到除了它自己的接口的所有处理器。