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    Logic verification system
    1.
    发明申请
    Logic verification system 审中-公开
    逻辑验证系统

    公开(公告)号：US20080306722A1

    公开(公告)日：2008-12-11

    申请号：US12068628

    申请日：2008-02-08

    申请人： Mototsugu Fujii ,  Osamu Tada ,  Kazunobu Morimoto ,  Akira Yamagiwa ,  Hisashi Nanao

    发明人： Mototsugu Fujii ,  Osamu Tada ,  Kazunobu Morimoto ,  Akira Yamagiwa ,  Hisashi Nanao

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5027

    摘要： There is provided a logic verification system having improved development time and design quality, in which all pins of an FPGA module are wired in direct between the FPGA module and a bridge circuit used in the verification processes of a logic simulator accelerator and a logic emulator, a cutting end of the verification object logic is assigned to an external interface connector of the FPGA module when the logic simulation is accelerated, and the correspondence between each pin of external interface connector of the FPGA module and logic signal is performed on the logic simulator on the general purpose processor.

    摘要翻译： 提供了具有改进的开发时间和设计质量的逻辑验证系统，其中FPGA模块的所有引脚直接连接在FPGA模块和用于逻辑模拟器加速器和逻辑仿真器的验证过程中的桥接电路之间， 当逻辑模拟被加速时，验证对象逻辑的切割端被分配给FPGA模块的外部接口连接器，并且在逻辑模拟器上执行FPGA模块的外部接口连接器的每个引脚与逻辑信号之间的对应关系 通用处理器。

    Logic dividing method, logic dividing system and recording medium for storing logic dividing program
    2.
    发明授权
    Logic dividing method, logic dividing system and recording medium for storing logic dividing program 失效
    逻辑分割方法，逻辑分割系统和用于存储逻辑分割程序的记录介质

    公开(公告)号：US06564367B1

    公开(公告)日：2003-05-13

    申请号：US09619636

    申请日：2000-07-19

    申请人： Mototsugu Fujii ,  Kazunobu Morimoto ,  Osamu Tada

    发明人： Mototsugu Fujii ,  Kazunobu Morimoto ,  Osamu Tada

    IPC分类号： G06F1750

    CPC分类号： G06F17/5027

    摘要： Logic emulation according to the present invention is aimed at an object to provide a logic dividing and module wiring system for operating logic related to external interface signals and interface signals among circuits obtained as a result of division or a logic circuit at a high speed. In a logic emulation system, information on assignments of external interface signals of logic to connector pins is read in during division of the logic. Logic related to an external interface signal assigned to a connector pin is assigned to a field programmable gate array directly connected to the connector pin. In addition, delays are checked after the division of a logic circuit in order to determine the level of delay criticality of each interface signal between field programmable gate arrays. Wiring of a module is then carried out in accordance with the levels of criticality.

    摘要翻译： 根据本发明的逻辑仿真的目的是提供一种逻辑分配和模块布线系统，用于在与作为分割的结果获得的电路中的外部接口信号和接口信号之间进行操作逻辑，或者以高速度进行逻辑电路。 在逻辑仿真系统中，在逻辑分配期间读入关于逻辑到连接器引脚的外部接口信号的分配的信息。 与分配给连接器引脚的外部接口信号相关的逻辑被分配给直接连接到连接器引脚的现场可编程门阵列。 此外，在分离逻辑电路之后检查延迟，以便确定现场可编程门阵列之间每个接口信号的延迟关键度的水平。 然后根据临界水平执行模块的接线。

    Program data creating method and apparatus for use with programmable devices in a logic emulation system
    3.
    发明授权
    Program data creating method and apparatus for use with programmable devices in a logic emulation system 失效
    用于与逻辑仿真系统中的可编程器件一起使用的程序数据创建方法和装置

    公开(公告)号：US5911061A

    公开(公告)日：1999-06-08

    申请号：US692626

    申请日：1996-08-06

    申请人： Tatsuya Tochio ,  Osamu Tada ,  Toshio Oguma ,  Kazunobu Morimoto ,  Mototsugu Fujii

    发明人： Tatsuya Tochio ,  Osamu Tada ,  Toshio Oguma ,  Kazunobu Morimoto ,  Mototsugu Fujii

    IPC分类号： G05B19/05 ,  G06F17/50 ,  G06F17/00

    CPC分类号： G06F17/5027 ,  G06F17/5054

    摘要： A program data creating method and apparatus for use with programmable devices in a logic emulation system provides high-speed logic emulation of an LSI for logic and function verification. The logic data defining the logic circuits of the LSI is divided into a plurality of unit blocks in a layout analogous to the floor plan represented by floor plan information for the LSI. The unit blocks are allocated to the programmable devices automatically. The names of the signals defined within the design data regarding the LSI are made to correspond with the names of the signals in effect when the design data is deployed within the programmable devices, after optimization of the logic. This allows the program data for the programmable devices to be created and corrected using the signal names as set forth in the design data.

    摘要翻译： 用于逻辑仿真系统中的可编程器件的程序数据创建方法和装置提供用于逻辑和功能验证的LSI的高速逻辑仿真。 定义LSI的逻辑电路的逻辑数据以类似于用于LSI的平面图信息表示的平面图的布局被划分为多个单元块。 单位块自动分配给可编程设备。 在设计数据中定义的关于LSI的信号的名称在逻辑优化之后被设计成与设计数据部署在可编程设备内部时有效的信号的名称相对应。 这允许使用设计数据中所阐述的信号名称来创建和校正可编程器件的程序数据。

    Design support system and method therefor
    4.
    发明授权
    Design support system and method therefor 失效
    设计支持系统及其方法

    公开(公告)号：US5961557A

    公开(公告)日：1999-10-05

    申请号：US654762

    申请日：1996-05-29

    申请人： Kazunobu Morimoto ,  Shun Ishiyama ,  Osamu Tada ,  Satoshi Fujiwara

    发明人： Kazunobu Morimoto ,  Shun Ishiyama ,  Osamu Tada ,  Satoshi Fujiwara

    IPC分类号： G06F17/50 ,  G06G7/78

    CPC分类号： G06F17/5022

    摘要： A design support system for executing logic verification so as to perform work management, progress state management and logic quality management efficiently in a logic verification process and so as to improve the man-hour for development and the throughput of computer resources. For every verification item to be executed, management information including a verification item number for identifying a verification item, confirmation information for indicating the fact that no failure has been confirmed in the verification item, a prerequisite verification item number for identifying another verification item required to be confirmed as a prerequisite for the verification item is stored in a memory of the system. Before execution of logic simulation which is performed by giving test data for logic verification of the design data to the design data as a subject of logic verification, data in the memory are searched so that logic simulation is executed in the case where all verification items as prerequisites for verification items to be executed have been already confirmed.

    摘要翻译： 一种用于执行逻辑验证的设计支持系统，以便在逻辑验证过程中有效地执行工作管理，进度状态管理和逻辑质量管理，从而提高计算机资源的开发工时和吞吐量。 对于要执行的每个验证项目，包括用于识别验证项目的验证项目编号的管理信息，用于指示在验证项目中未确认故障的事实的确认信息，用于识别所需的另一验证项目的前提验证项目号码 被确认为验证项目的先决条件存储在系统的存储器中。 在通过将设计数据的逻辑验证测试数据作为逻辑验证的对象的设计数据执行的逻辑仿真执行之前，搜索存储器中的数据，以便在所有验证项目为 要确认的验证项目的先决条件已经确认。

    Portable trimmer and handle-bar therefor
    6.
    发明授权
    Portable trimmer and handle-bar therefor 失效
    便携式修剪器和手柄

    公开(公告)号：US06082087A

    公开(公告)日：2000-07-04

    申请号：US972016

    申请日：1997-11-17

    申请人： Osamu Tada ,  Takayuki Yamamoto

    发明人： Osamu Tada ,  Takayuki Yamamoto

    IPC分类号： A01D34/68 ,  A01D34/90 ,  A01G3/06 ,  A01D34/67 ,  A01D34/82

    CPC分类号： A01D34/902 ,  A01G3/06 ,  Y10S56/18

    摘要： A portable trimmer has a supporting tube extending straight forward from an engine at its rearward end to a cutting device at a forward end. A handle-bar is mounted on a middle portion of the supporting tube at an intersecting point. First and second grips extend upwardly from two corresponding ends of the handle-bar. The handle-bar has a first portion extending from an intersecting point to the first grip, and a second portion extending from the intersecting point to the second grip. The first portion extends across a width of an operator's body, and is bent in a rearward direction. The supporting tube has an inclination with respect to a phantom line connecting the first and second grips such that said cutting device is located in front of a center of the operator's body when the operator holds the grips in a natural posture. This portable trimmer increases the area in which weeds can be cut in a single movement, and provides for easy handling.

    摘要翻译： 便携式修剪器具有支撑管，该支撑管在其后端从发动机直接向前延伸到前端处的切割装置。 手柄在交叉点安装在支撑管的中间部分。 第一和第二把手从把手杆的两个对应的端部向上延伸。 把手杆具有从交叉点延伸到第一把手的第一部分和从交叉点延伸到第二把手的第二部分。 第一部分延伸穿过操作者身体的宽度，并沿向后的方向弯曲。 支撑管相对于连接第一和第二把手的虚线具有倾斜度，使得当操作者以自然的姿势握住把手时，所述切割装置位于操作者身体的中心的前方。 这种便携式修剪器增加了在单个运动中可以切割杂草的区域，并且提供容易的处理。

    Logic division apparatus
    7.
    发明授权
    Logic division apparatus 失效
    逻辑分割装置

    公开(公告)号：US5875116A

    公开(公告)日：1999-02-23

    申请号：US588236

    申请日：1996-01-18

    申请人： Toshio Oguma ,  Osamu Tada

    发明人： Toshio Oguma ,  Osamu Tada

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054

    摘要： The electronic circuits of a large-scale ASIC or logic device are assigned to a plurality of programmable chips with logic block division that enables the finished circuits to operate at appropriate timings. A logic division processing unit divides the electronic circuits into a plurality of groups for automatic assignment to a plurality of programmable chips. A checking unit determines whether the designated logic blocks are accommodated in one programmable chip, and a division processing unit determines which logic blocks are to be assigned and the order of assignment priorities when the designated logic blocks are not all accommodated in the same programmable chip.

    摘要翻译： 大规模ASIC或逻辑器件的电子电路被分配给具有逻辑块划分的多个可编程芯片，使得成品电路能够在适当的定时运行。 逻辑分割处理单元将电子电路分为多个组，用于自动分配给多个可编程芯片。 检查单元确定指定的逻辑块是否被容纳在一个可编程芯片中，并且分割处理单元确定哪个逻辑块将被分配，并且当指定的逻辑块不全部被容纳在相同的可编程芯片中时，分配优先级的顺序。

    APPARATUS FOR PRODUCTION OF METALLIC SLAB USING ELECTRON BEAM, AND PROCESS FOR PRODUCTION OF METALLIC SLAB USING THE APPARATUS
    10.
    发明申请
    APPARATUS FOR PRODUCTION OF METALLIC SLAB USING ELECTRON BEAM, AND PROCESS FOR PRODUCTION OF METALLIC SLAB USING THE APPARATUS 审中-公开
    用于生产使用电子束的金属板的装置以及使用装置生产金属板的方法

    公开(公告)号：US20110308760A1

    公开(公告)日：2011-12-22

    申请号：US13148377

    申请日：2009-02-08

    申请人： Hisamune Tanaka ,  Osamu Tada ,  Takashi Oda ,  Yoshimasa Miyazaki ,  Kazuhiro Takahashi

    发明人： Hisamune Tanaka ,  Osamu Tada ,  Takashi Oda ,  Yoshimasa Miyazaki ,  Kazuhiro Takahashi

    IPC分类号： B22D25/06 ,  F27B3/08 ,  B22D45/00

    CPC分类号： C22B9/228 ,  B22D11/00 ,  B22D11/041 ,  B22D11/05 ,  B22D11/113 ,  C22B34/1295 ,  C22B34/24

    摘要： An apparatus and method allows the width of high-melting temperature reactive metallic slabs produced in an electron beam melting furnace to be easily changed. The apparatus for production of the metallic slabs by the electron beam melting has a metal melting part and a metal extraction part mutually separated by an air tight valve; a metal melting part has a melting chamber, electron gun, hearth, a mold of variable wall distance, and an air tight valve; and the metal extraction part has a slab chamber, an extraction base, an extracting shaft, and an drive unit for extracting the metal slab. The method for production of the metallic slab using this apparatus has a step of pulling a previous metallic slab produced in the rectangular mold out of the rectangular mold, a step of moving the short mold wall(s) of the rectangular mold to change the width of the rectangular mold, and a step of producing a subsequent metallic slab.

    摘要翻译： 一种装置和方法允许容易地改变在电子束熔化炉中产生的高熔点温度的反应性金属板的宽度。 通过电子束熔融制造金属板的装置具有通过气密阀相互分离的金属熔化部分和金属提取部分; 金属熔化部分具有熔化室，电子枪，炉床，可变壁距离的模具和气密阀; 并且金属提取部具有板状室，提取基座，提取轴和用于提取金属板的驱动单元。 使用该装置制造金属板的方法具有将矩形模具中生产的以前的金属板拉出矩形模具的步骤，移动矩形模具的短模具壁以改变宽度的步骤 以及制造后续的金属板坯的步骤。