公开(公告)号：US06262909B1

公开(公告)日：2001-07-17

申请号：US09343564

申请日：1999-06-30

Applicant: Hoon Woo Kye ,  Woo Soon Kang

Inventor： Hoon Woo Kye ,  Woo Soon Kang

IPC: G11C1122

CPC classification number: G11C11/22

Abstract: Disclosed is a ferroelectric memory device having a memory cell structure where a plurality of ferroelectric capacitor are connected to one switching transistor, and a plurality of data are outputted according to one address input. The ferroelectric memory device comprises a plurality of word lines for driving a corresponding memory cell in accordance with an input address; a plurality of bit lines crossing said word lines, respectively; a plurality of switching transistors connected both to the bit lines and the word lines, respectively; and a plurality of dielectric capacitors wherein one end is coupled in common to a node of the switching transistor, respectively; wherein a plurality of output data are outputted by selecting a memory cell including at least one switching transistor corresponding to the plurality of switching transistors, and to the plurality of dielectric capacitors.

Abstract translation: 公开了具有存储单元结构的铁电存储器件，其中多个铁电电容器连接到一个开关晶体管，并且根据一个地址输入输出多个数据。 铁电存储器件包括用于根据输入地址驱动相应的存储器单元的多个字线; 分别与所述字线交叉的多个位线; 分别连接到位线和字线的多个开关晶体管; 以及多个介质电容器，其中一端分别耦合到所述开关晶体管的节点; 其中通过选择包括与所述多个开关晶体管对应的至少一个开关晶体管的存储单元以及所述多个介质电容器来输出多个输出数据。

公开(公告)号：US6058049A

公开(公告)日：2000-05-02

申请号：US105591

申请日：1998-06-26

Applicant: Hoon Woo Kye ,  Woo Soon Kang

Inventor： Hoon Woo Kye ,  Woo Soon Kang

IPC: G11C16/06 ,  G11C5/14 ,  G11C11/22 ,  G11C11/34

CPC classification number: G11C11/22 ,  G11C5/147

Abstract: The present invention provides a reference voltage generating circuit for generating a stable reference voltage and having a long life time, and the reference voltage generating circuit for generating a reference voltage of a ferroelectric memory device having a plurality of bit line pairs, including: a first and second reference word line; a first dummy block comprising a plurality of switching transistors and a plurality of ferroelectric capacitors, wherein gates of the switching transistors are coupled to the first reference word line and drains/sources of the switching transistors are coupled to a bit line of one of the bit line pairs; a second dummy block comprising a plurality of switching transistors and a plurality of ferroelectric capacitors, wherein gates of the switching transistors are coupled to a second reference word line and drains/sources of the switching transistors are coupled to a bit bar line of one of the bit line pairs; and a reference plate line commonly coupled to the ferroelectric capacitors of both of the dummy blocks.

Abstract translation: 本发明提供一种用于产生稳定的参考电压并具有长寿命的参考电压产生电路，以及用于产生具有多个位线对的铁电存储器件的参考电压的参考电压产生电路，包括：第一 和第二参考字线; 第一虚拟块，包括多个开关晶体管和多个铁电电容器，其中开关晶体管的栅极耦合到第一参考字线，并且开关晶体管的漏极/源极耦合到位中的一个的位线 线对 包括多个开关晶体管和多个铁电电容器的第二虚拟块，其中所述开关晶体管的栅极耦合到第二参考字线，并且所述开关晶体管的漏极/源极耦合到所述开关晶体管中的一个的位线 位线对; 以及通常耦合到两个虚拟块的铁电电容器的参考板线。

公开(公告)号：US06175528B1

公开(公告)日：2001-01-16

申请号：US09475280

申请日：1999-12-30

Applicant: Hoon-Woo Kye

Inventor： Hoon-Woo Kye

IPC: G11C700

CPC classification number: G11C29/789

Abstract: A redundancy address bit programming circuit including a redundancy memory cell, includes: program pads for providing signals to first and second program nodes; a ferroelectric capacitor programmed according to a bit value corresponding to a defected address, coupled between the first and second nodes; a load capacitor coupled between the second program node and a ground; a power-up signal generator means for generating a power-up signal to be coupled to the first program node, wherein the power-up signal follows a level of a power signal at a beginning of a power signal supply, and is maintained as a ground level during a stable level state of the power signal supply; a latch means for latching the second program node signal at the beginning of the power signal supply and outputting a latched signal during the stable level state of the power signal supply; and a multiplexer for selectively outputting one of an address bit signal and a reversed address bit signal in response to the latched signal.

Abstract translation: 包括冗余存储单元的冗余地址位编程电路包括：用于向第一和第二程序节点提供信号的编程焊盘; 根据与缺陷地址相对应的位值编程的铁电电容器，耦合在第一和第二节点之间; 耦合在第二节目节点和地之间的负载电容器; 上电信号发生器装置，用于产生要耦合到第一节目节点的上电信号，其中上电信号在功率信号提供开始时跟随功率信号的电平，并保持为 在电源信号供电的稳定电平状态下的地电平; 锁存装置，用于在电源信号提供开始时锁存第二节目节点信号，并在电源信号供应的稳定电平状态期间输出锁存信号; 以及多路复用器，用于响应于锁存信号选择性地输出地址位信号和反转地址位信号中的一个。