公开(公告)号：US06262909B1

公开(公告)日：2001-07-17

申请号：US09343564

申请日：1999-06-30

Applicant: Hoon Woo Kye ,  Woo Soon Kang

Inventor： Hoon Woo Kye ,  Woo Soon Kang

IPC: G11C1122

CPC classification number: G11C11/22

Abstract: Disclosed is a ferroelectric memory device having a memory cell structure where a plurality of ferroelectric capacitor are connected to one switching transistor, and a plurality of data are outputted according to one address input. The ferroelectric memory device comprises a plurality of word lines for driving a corresponding memory cell in accordance with an input address; a plurality of bit lines crossing said word lines, respectively; a plurality of switching transistors connected both to the bit lines and the word lines, respectively; and a plurality of dielectric capacitors wherein one end is coupled in common to a node of the switching transistor, respectively; wherein a plurality of output data are outputted by selecting a memory cell including at least one switching transistor corresponding to the plurality of switching transistors, and to the plurality of dielectric capacitors.

Abstract translation: 公开了具有存储单元结构的铁电存储器件，其中多个铁电电容器连接到一个开关晶体管，并且根据一个地址输入输出多个数据。 铁电存储器件包括用于根据输入地址驱动相应的存储器单元的多个字线; 分别与所述字线交叉的多个位线; 分别连接到位线和字线的多个开关晶体管; 以及多个介质电容器，其中一端分别耦合到所述开关晶体管的节点; 其中通过选择包括与所述多个开关晶体管对应的至少一个开关晶体管的存储单元以及所述多个介质电容器来输出多个输出数据。

公开(公告)号：US06256260B1

公开(公告)日：2001-07-03

申请号：US09570729

申请日：2000-05-12

Applicant: Young-Bo Shim ,  Woo-Soon Kang

Inventor： Young-Bo Shim ,  Woo-Soon Kang

IPC: G11C800

CPC classification number: G11C7/109 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/225 ,  G11C8/06 ,  G11C11/4093

Abstract: A synchronous semiconductor memory device having a plurality of external signal input buffer and a plurality of latch circuits, includes: a clock buffer for receiving an external clock signal to generate a buffered clock signal; a chip select buffer for receiving an external chip select signal and the buffered clock signal from said clock buffer to generate a buffered chip select signal, an inverted buffered chip select signal and a latch control signal, wherein the latch control signal is activated when the external clock signal is at the rising edge and the external chip select signal is low; a plurality of external signal buffers for receiving external signals to generate buffered signals and inverted buffered signals; and a plurality of latch circuits for latching and outputting the buffered signals and the inverted buffer signals to an internal logic circuit in response to the latch control signal.

Abstract translation: 一种具有多个外部信号输入缓冲器和多个锁存电路的同步半导体存储器件，包括：时钟缓冲器，用于接收外部时钟信号以产生缓冲的时钟信号; 芯片选择缓冲器，用于接收来自所述时钟缓冲器的外部芯片选择信号和缓冲的时钟信号，以产生缓冲芯片选择信号，反相缓冲芯片选择信号和锁存控制信号，其中当外部 时钟信号处于上升沿，外部芯片选择信号为低电平; 多个外部信号缓冲器，用于接收外部信号以产生缓冲信号和反相缓冲信号; 以及多个锁存电路，用于响应于锁存控制信号而将缓冲信号和反相缓冲器信号锁存并输出到内部逻辑电路。

公开(公告)号：US6058049A

公开(公告)日：2000-05-02

申请号：US105591

申请日：1998-06-26

Applicant: Hoon Woo Kye ,  Woo Soon Kang

Inventor： Hoon Woo Kye ,  Woo Soon Kang

IPC: G11C16/06 ,  G11C5/14 ,  G11C11/22 ,  G11C11/34

CPC classification number: G11C11/22 ,  G11C5/147

Abstract: The present invention provides a reference voltage generating circuit for generating a stable reference voltage and having a long life time, and the reference voltage generating circuit for generating a reference voltage of a ferroelectric memory device having a plurality of bit line pairs, including: a first and second reference word line; a first dummy block comprising a plurality of switching transistors and a plurality of ferroelectric capacitors, wherein gates of the switching transistors are coupled to the first reference word line and drains/sources of the switching transistors are coupled to a bit line of one of the bit line pairs; a second dummy block comprising a plurality of switching transistors and a plurality of ferroelectric capacitors, wherein gates of the switching transistors are coupled to a second reference word line and drains/sources of the switching transistors are coupled to a bit bar line of one of the bit line pairs; and a reference plate line commonly coupled to the ferroelectric capacitors of both of the dummy blocks.

Abstract translation: 本发明提供一种用于产生稳定的参考电压并具有长寿命的参考电压产生电路，以及用于产生具有多个位线对的铁电存储器件的参考电压的参考电压产生电路，包括：第一 和第二参考字线; 第一虚拟块，包括多个开关晶体管和多个铁电电容器，其中开关晶体管的栅极耦合到第一参考字线，并且开关晶体管的漏极/源极耦合到位中的一个的位线 线对 包括多个开关晶体管和多个铁电电容器的第二虚拟块，其中所述开关晶体管的栅极耦合到第二参考字线，并且所述开关晶体管的漏极/源极耦合到所述开关晶体管中的一个的位线 位线对; 以及通常耦合到两个虚拟块的铁电电容器的参考板线。