公开(公告)号：US06859109B1

公开(公告)日：2005-02-22

申请号：US10250000

申请日：2003-05-27

Applicant: Gerry C. T. Leung ,  Howard C. Luong

Inventor： Gerry C. T. Leung ,  Howard C. Luong

IPC: H03B5/12 ,  H03L7/099 ,  H03L7/183 ,  H03B27/00

CPC classification number: H03L7/099 ,  H03B5/1215 ,  H03B5/1228 ,  H03B2200/0078 ,  H03L7/183

Abstract: A phase-locked loop (PLL) has an analog divider in the feedback path that receives either the in-phase or quadrature-phase pair of outputs from a voltage-controlled oscillator (VCO) while the other pair, 90-degree out-of-phase, of outputs from the VCO is used for the PLL output. Phases between the PLL's input and output are inherently aligned. The analog output of the analog divider is converted to a digital clock signal and applied to a cascade of digital dividers to generate a reduced feedback clock. The reduced feedback clock is applied to the D input and the digital clock signal is applied to the clock input of a pseudo D-flip-flop that drives the feedback input of a phase-frequency detector that drives the charge pump to the VCO input. Another cascade of digital dividers and pseudo D-flip-flop re-align the reference clock input to the phase-frequency detector. Analog and digital re-alignment circuits reduce internal skew.

Abstract translation: 锁相环（PLL）在反馈路径中具有模拟分频器，其接收来自压控振荡器（VCO）的同相或正交相输出对，而另一对，90度外 VCO的输出相位用于PLL输出。 PLL的输入和输出之间的相位固有地对齐。 模拟分频器的模拟输出转换为数字时钟信号，并应用于级联的数字分频器以产生减小的反馈时钟。 减小的反馈时钟被施加到D输入，并且数字时钟信号被施加到伪D触发器的时钟输入，该伪D触发器驱动将电荷泵驱动到VCO输入的相位频率检测器的反馈输入。 数字分频器和伪D触发器的另一个级联将参考时钟输入重新对准相位频率检测器。 模拟和数字重新对准电路减少内部偏移。