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    I-R voltage drop screening when executing a memory built-in self test
    1.
    发明授权
    I-R voltage drop screening when executing a memory built-in self test 有权
    执行存储器内置自检时的I-R电压降屏蔽

    公开(公告)号：US08341476B1

    公开(公告)日：2012-12-25

    申请号：US12607841

    申请日：2009-10-28

    申请人： Hsiu-Ping Peng ,  Jae-Hong Lee

    发明人： Hsiu-Ping Peng ,  Jae-Hong Lee

    IPC分类号： G01R31/28 ,  G11C29/00

    CPC分类号： G11C5/025 ,  G11C29/12 ,  G11C29/50

    摘要： A built-in self test (BIST) method and system for testing a memory included on an integrated circuit includes activating a component of the integrated circuit, partitioning the memory into a first part for use by non-BIST components and second part for BIST, and executing BIST on the second part of the memory while the component is operating. While the BIST is executing, the non-BIST components can access the first part of the memory and perform normal functional operations. The BIST method and system finds memory faults that are related to an I-R voltage drop due to the physical placement of the memory relative to power supply sources.

    摘要翻译： 用于测试集成电路中包括的存储器的内置自测（BIST）方法和系统包括激活集成电路的组件，将存储器分为第一部分供非BIST组件和第二部分用于BIST， 并在组件运行时在存储器的第二部分执行BIST。 当BIST正在执行时，非BIST组件可以访问存储器的第一部分并执行正常的功能操作。 BIST方法和系统发现由于存储器相对于电源的物理放置而与I-R电压降有关的存储器故障。