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    Frequency Divider and Phase Locked Loop Including the Same
    2.
    发明申请
    Frequency Divider and Phase Locked Loop Including the Same 有权
    分频器和锁相环包括它

    公开(公告)号：US20130002319A1

    公开(公告)日：2013-01-03

    申请号：US13535424

    申请日：2012-06-28

    申请人： Hwan-Seok Yeo ,  Ji-Hyun Kim

    发明人： Hwan-Seok Yeo ,  Ji-Hyun Kim

    IPC分类号： H03K23/52 ,  H03L7/089

    CPC分类号： H03K23/52 ,  H03K23/667 ,  H03L7/089 ,  H03L7/18

    摘要： A frequency includes a first edge detection unit configured to generate a first count signal responsive to detecting first edges of an input signal and a second edge detection unit configured to generate a second count signal responsive to detecting the first edges of the input signal in a first operation mode and to generate the second count signal responsive to detecting second edges of the input signal in a second operation mode. One of the first and second edges is a rising edge and the other of the first and second edges is a falling edge. A pulse triggered buffer unit generates an output signal responsive to the first and second count signals. The output signal is divided by a target division ratio with respect to the input signal that is an odd number division ratio in one mode and an even number division ratio in the other mode.

    摘要翻译： 频率包括：第一边缘检测单元，被配置为响应于检测到输入信号的第一边缘而产生第一计数信号;以及第二边缘检测单元，被配置为产生第二计数信号，所述第二边缘检测单元响应于检测到第一 并且响应于在第二操作模式中检测到输入信号的第二边缘而产生第二计数信号。 第一和第二边缘中的一个是上升沿，第一和第二边缘中的另一个是下降沿。 脉冲触发缓冲器单元响应于第一和第二计数信号产生输出信号。 输出信号相对于作为一个模式的奇数分频比的输入信号和另一模式下的偶数分频比除以目标分频比。

    Frequency divider and phase locked loop including the same
    4.
    发明授权
    Frequency divider and phase locked loop including the same 有权
    分频器和锁相环包括相同的

    公开(公告)号：US08736317B2

    公开(公告)日：2014-05-27

    申请号：US13535424

    申请日：2012-06-28

    申请人： Hwan-Seok Yeo ,  Ji-Hyun Kim

    发明人： Hwan-Seok Yeo ,  Ji-Hyun Kim

    IPC分类号： H03K23/00 ,  H03K21/00

    CPC分类号： H03K23/52 ,  H03K23/667 ,  H03L7/089 ,  H03L7/18

    摘要： A frequency includes a first edge detection unit configured to generate a first count signal responsive to detecting first edges of an input signal and a second edge detection unit configured to generate a second count signal responsive to detecting the first edges of the input signal in a first operation mode and to generate the second count signal responsive to detecting second edges of the input signal in a second operation mode. One of the first and second edges is a rising edge and the other of the first and second edges is a falling edge. A pulse triggered buffer unit generates an output signal responsive to the first and second count signals. The output signal is divided by a target division ratio with respect to the input signal that is an odd number division ratio in one mode and an even number division ratio in the other mode.

    摘要翻译： 频率包括：第一边缘检测单元，被配置为响应于检测到输入信号的第一边缘而产生第一计数信号;以及第二边缘检测单元，被配置为产生第二计数信号，所述第二边缘检测单元响应于检测到第一 并且响应于在第二操作模式中检测到输入信号的第二边缘而产生第二计数信号。 第一和第二边缘中的一个是上升沿，第一和第二边缘中的另一个是下降沿。 脉冲触发缓冲器单元响应于第一和第二计数信号产生输出信号。 输出信号相对于作为一个模式的奇数分频比的输入信号和另一模式下的偶数分频比除以目标分频比。

    DELAY LOCKED LOOP (DLL) CIRCUITS HAVING AN EXPANDED OPERATION RANGE AND METHODS OF OPERATING THE SAME
    5.
    发明申请
    DELAY LOCKED LOOP (DLL) CIRCUITS HAVING AN EXPANDED OPERATION RANGE AND METHODS OF OPERATING THE SAME 审中-公开
    具有扩展操作范围的延迟锁定环路（DLL）电路及其操作方法

    公开(公告)号：US20080252340A1

    公开(公告)日：2008-10-16

    申请号：US12099323

    申请日：2008-04-08

    申请人： Hwan-seok Yeo ,  Jin-ho Seo ,  Hong-june Park ,  Jun-hyun Bae

    发明人： Hwan-seok Yeo ,  Jin-ho Seo ,  Hong-june Park ,  Jun-hyun Bae

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/091

    摘要： Delay locked loop (DLL) circuits have a phase detector circuit that can detect a phase difference between an input clock signal and an output clock signal over a time period of 0T-2T. The delay applied to generate the output signal is adjusted based on the detected phase difference. A middle clock signal can be generated that has a phase that is between the input clock signal and the output clock signal. The phase detector circuit may be configured to detect the phase difference between the input clock signal and the output clock signal over the time period 0T-2T responsive to the middle clock signal.

    摘要翻译： 延迟锁定环（DLL）电路具有相位检测器电路，可在0T-2T的时间段内检测输入时钟信号和输出时钟信号之间的相位差。 基于检测到的相位差来调整用于产生输出信号的延迟。 可以产生具有在输入时钟信号和输出时钟信号之间的相位的中间时钟信号。 相位检测器电路可以被配置为响应于中间时钟信号在时间段0T-2T上检测输入时钟信号和输出时钟信号之间的相位差。