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    PREDICTION OF DYNAMIC CURRENT WAVEFORM AND SPECTRUM IN A SEMICONDUCTOR DEVICE
    2.
    发明申请
    PREDICTION OF DYNAMIC CURRENT WAVEFORM AND SPECTRUM IN A SEMICONDUCTOR DEVICE 有权
    在半导体器件中预测动态电流波形和光谱

    公开(公告)号：US20080288898A1

    公开(公告)日：2008-11-20

    申请号：US12116095

    申请日：2008-05-06

    申请人： Peter Boyle ,  Iliya G. Zamek ,  Zhe Li ,  Shishuang Sun ,  Bozidar Krsnik ,  James L. Drewniak

    发明人： Peter Boyle ,  Iliya G. Zamek ,  Zhe Li ,  Shishuang Sun ,  Bozidar Krsnik ,  James L. Drewniak

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  H05K1/0231 ,  H05K3/0005

    摘要： A method for determining a current spectrum for a circuit design is provided. The method includes determining timing characteristics and power consumption characteristics for the circuit design. From the timing characteristics and the power consumption characteristics a time domain current waveform is constructed. The time domain current waveform is then converted to a frequency domain current waveform. With the frequency domain waveform, one skilled in the art can then identify a location and an amount of decoupling capacitors for a printed circuit board housing the circuit design based on the frequency domain current waveform. A computing system configured to perform the method is also provided.

    摘要翻译： 提供了一种用于确定电路设计的当前频谱的方法。 该方法包括确定电路设计的时序特性和功耗特性。 从定时特性和功耗特性构建时域电流波形。 时域电流波形然后转换为频域电流波形。 利用频域波形，本领域技术人员可以基于频域电流波形来识别容纳电路设计的印刷电路板的去耦电容器的位置和量。 还提供了被配置为执行该方法的计算系统。

    Prediction of dynamic current waveform and spectrum in a semiconductor device
    3.
    发明授权
    Prediction of dynamic current waveform and spectrum in a semiconductor device 有权
    预测半导体器件中的动态电流波形和频谱

    公开(公告)号：US09038007B2

    公开(公告)日：2015-05-19

    申请号：US13365567

    申请日：2012-02-03

    申请人： Peter Boyle ,  Iliya G. Zamek

    发明人： Peter Boyle ,  Iliya G. Zamek

    IPC分类号： G06F17/50 ,  H05K3/00 ,  H05K1/02

    CPC分类号： G06F17/5036 ,  G06F2217/84 ,  H05K1/0231 ,  H05K3/0005

    摘要： A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing and power consumption characteristics. In one embodiment, timing characteristics are provided through a electronic design automation tool. The timing characteristics yield a current pulse time width. In another embodiment, power consumption characteristics are provided by an EDA tool. The power consumption characteristics yield a current pulse amplitude. The shape of the current pulse is obtained by incrementally processing a power analyzer tool over relatively small time increments over one or more clock cycles while capturing the switching nodes of a simulation of the circuit design for each time increment. In one embodiment, the time increments are one nanosecond or less.

    摘要翻译： 提供了用于精确地确定用于电路设计的当前频谱中的电流形状的方法。 该方法包括确定时序和功耗特征。 在一个实施例中，通过电子设计自动化工具提供定时特性。 时序特性产生电流脉冲时间宽度。 在另一个实施例中，功耗特性由EDA工具提供。 功耗特性产生电流脉冲幅度。 当前脉冲的形状是通过在一个或多个时钟周期上相对较小的时间增量来逐步处理功率分析器工具而获得的，同时在每个时间增量的同时捕获电路设计的模拟的切换节点。 在一个实施例中，时间增量为一纳秒或更小。

    Prediction of dynamic current waveform and spectrum in a semiconductor device
    4.
    发明授权
    Prediction of dynamic current waveform and spectrum in a semiconductor device 有权
    预测半导体器件中的动态电流波形和频谱

    公开(公告)号：US08132137B1

    公开(公告)日：2012-03-06

    申请号：US12268365

    申请日：2008-11-10

    申请人： Peter Boyle ,  Iliya G. Zamek

    发明人： Peter Boyle ,  Iliya G. Zamek

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  G06F2217/84 ,  H05K1/0231 ,  H05K3/0005

    摘要： A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing characteristics and power consumption characteristics for the circuit design. In one embodiment, the timing characteristics are provided through a electronic design automation tool. The timing characteristics yield a current pulse time width. In another embodiment, the power consumption characteristics are provided by an EDA tool. The power consumption characteristics yield a current pulse amplitude. The shape of the current pulse is obtained by incrementally processing a power analyzer tool over relatively small time increments over one or more clock cycles while capturing the switching nodes of a simulation of the circuit design for each time increment. In one embodiment, the time increments are one nanosecond or less. From the timing characteristics and the power consumption characteristics a time domain current waveform is constructed, which can be converted to the frequency domain.

    摘要翻译： 提供了用于精确地确定用于电路设计的当前频谱中的电流形状的方法。 该方法包括确定电路设计的时序特性和功耗特性。 在一个实施例中，通过电子设计自动化工具提供定时特性。 时序特性产生电流脉冲时间宽度。 在另一实施例中，功耗特性由EDA工具提供。 功耗特性产生电流脉冲幅度。 当前脉冲的形状是通过在一个或多个时钟周期上相对较小的时间增量来逐步处理功率分析器工具而获得的，同时在每个时间增量的同时捕获电路设计的模拟的切换节点。 在一个实施例中，时间增量为一纳秒或更小。 从定时特性和功耗特性构成时域电流波形，可以将其转换为频域。

    Methods for reducing power supply simultaneous switching noise
    5.
    发明授权
    Methods for reducing power supply simultaneous switching noise 失效
    降低电源同时开关噪声的方法

    公开(公告)号：US07669151B1

    公开(公告)日：2010-02-23

    申请号：US11715593

    申请日：2007-03-07

    申请人： Peter Boyle ,  Iliya G. Zamek ,  Zhe Li ,  Lawrence David Smith

    发明人： Peter Boyle ,  Iliya G. Zamek ,  Zhe Li ,  Lawrence David Smith

    IPC分类号： G06F17/50 ,  G06F19/00

    CPC分类号： G06F17/5045 ,  G06F1/10 ,  G06F1/12

    摘要： Computer-aided design tools analyze a custom logic design for a programmable logic device integrated circuit. The tools identify distinct clock domains in the design. The tools also identify which of the clock domains are synchronous. The tools examine the synchronous clock domains to determine which of the clock domains have required fixed phase relationships. Clocks for clock domains that do not have required fixed relationships can be adjusted in phase to minimize power supply simultaneous switching noise. Noise may be minimized by making clock phase adjustments using a programmable phase-locked loop circuit.

    摘要翻译： 计算机辅助设计工具分析可编程逻辑器件集成电路的定制逻辑设计。 这些工具在设计中识别不同的时钟域。 这些工具还确定哪些时钟域是同步的。 这些工具检查同步时钟域，以确定哪些时钟域需要固定的相位关系。 不需要固定关系的时钟域的时钟可以同步调整，以最大限度地减少电源同时开关噪声。 通过使用可编程锁相环路电路进行时钟相位调整可以使噪声最小化。

    PREDICTION OF DYNAMIC CURRENT WAVEFORM AND SPECTRUM IN A SEMICONDUCTOR DEVICE
    6.
    发明申请
    PREDICTION OF DYNAMIC CURRENT WAVEFORM AND SPECTRUM IN A SEMICONDUCTOR DEVICE 审中-公开
    在半导体器件中预测动态电流波形和光谱

    公开(公告)号：US20120198410A1

    公开(公告)日：2012-08-02

    申请号：US13365567

    申请日：2012-02-03

    申请人： Peter Boyle ,  Iliya G. Zamek

    发明人： Peter Boyle ,  Iliya G. Zamek

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  G06F2217/84 ,  H05K1/0231 ,  H05K3/0005

    摘要： A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing and power consumption characteristics. In one embodiment, timing characteristics are provided through a electronic design automation tool. The timing characteristics yield a current pulse time width. In another embodiment, power consumption characteristics are provided by an EDA tool. The power consumption characteristics yield a current pulse amplitude. The shape of the current pulse is obtained by incrementally processing a power analyzer tool over relatively small time increments over one or more clock cycles while capturing the switching nodes of a simulation of the circuit design for each time increment. In one embodiment, the time increments are one nanosecond or less.

    摘要翻译： 提供了用于精确地确定用于电路设计的当前频谱中的电流形状的方法。 该方法包括确定时序和功耗特征。 在一个实施例中，通过电子设计自动化工具提供定时特性。 时序特性产生电流脉冲时间宽度。 在另一个实施例中，功耗特性由EDA工具提供。 功耗特性产生电流脉冲幅度。 当前脉冲的形状是通过在一个或多个时钟周期上相对较小的时间增量来逐步处理功率分析器工具而获得的，同时在每个时间增量的同时捕获电路设计的模拟的切换节点。 在一个实施例中，时间增量为一纳秒或更小。

    Integrated circuits with jitter-reducing balancing logic
    7.
    发明授权
    Integrated circuits with jitter-reducing balancing logic 有权
    具有抖动平衡逻辑的集成电路

    公开(公告)号：US07683659B1

    公开(公告)日：2010-03-23

    申请号：US12060791

    申请日：2008-04-01

    申请人： Iliya G. Zamek ,  Nafira Daud ,  Peter Boyle ,  Eugene V. Gomez

    发明人： Iliya G. Zamek ,  Nafira Daud ,  Peter Boyle ,  Eugene V. Gomez

    IPC分类号： H03K17/16 ,  H03K19/003

    CPC分类号： H03K19/00369 ,  G06F2217/82

    摘要： Integrated circuits contain core logic that is powered using a power supply signal. The core logic contains simultaneously switching circuitry. The simultaneously switching circuitry contributes to noise on the power supply signal. Balancing circuitry may be provided on the integrated circuit to compensate for the simultaneously switching circuitry in the core logic. The balancing circuitry may receive an input signal that is out of phase with respect to the input to the core logic. As the balancing circuitry switches out of phase with the simultaneously switching circuitry of the core logic, the noise contribution from the core logic is compensated and power supply noise on the power supply signal is minimized.

    摘要翻译： 集成电路包含使用电源信号供电的核心逻辑。 核心逻辑包含同时开关电路。 同时开关电路有助于电源信号上的噪声。 可以在集成电路上提供平衡电路以补偿核心逻辑中的同时开关电路。 平衡电路可以接收相对于核心逻辑的输入而异相的输入信号。 由于平衡电路与核心逻辑的同时开关电路异相切换，所以来自核心逻辑的噪声贡献被补偿并且电源信号上的电源噪声被最小化。

    Method and apparatus for predicting system noise
    8.
    发明授权
    Method and apparatus for predicting system noise 有权
    用于预测系统噪声的方法和装置

    公开(公告)号：US07454301B1

    公开(公告)日：2008-11-18

    申请号：US11465725

    申请日：2006-08-18

    申请人： Nafira Daud ,  Iliya G. Zamek ,  Peter Boyle

    发明人： Nafira Daud ,  Iliya G. Zamek ,  Peter Boyle

    IPC分类号： H03K1/04

    CPC分类号： G01R31/31709 ,  H04L1/205

    摘要： A jitter calculator engine that includes a core effects module, an input/output (I/O) module, and a phase lock loop (PLL) module is provided. The core effects module estimates core jitter caused by noise effects impacting a core clock network. The I/O module estimates I/O input pin switching effects on a clock network input signal. In one embodiment, the I/O module identifies a relative frequency of switching by I/O pins in the circuit design. The PLL module estimates an effect of a PLL on a signal delivered to the PLL from an I/O pin. The PLL module accounts for I/O input pin switching effects and core jitter. The jitter calculator engine may be in communication with a database and the different designs evaluated may be stored in the database so that the database becomes a repository for the different designs and may provide useful information for future designs.

    摘要翻译： 提供了包括核心效果模块，输入/输出（I / O）模块和锁相环（PLL）模块）的抖动计算器引擎。 核心效应模块估计由影响核心时钟网络的噪声影响引起的核心抖动。 I / O模块估计I / O输入引脚切换对时钟网络输入信号的影响。 在一个实施例中，I / O模块识别在电路设计中由I / O引脚切换的相对频率。 PLL模块估计PLL对从I / O引脚传送到PLL的信号的影响。 PLL模块考虑到I / O输入引脚切换效应和内核抖动。 抖动计算器引擎可以与数据库通信，并且评估的不同设计可以存储在数据库中，使得数据库成为不同设计的存储库，并且可以为将来的设计提供有用的信息。