System for recovering from a concurrent branch target buffer read with a
write allocation by invalidating and then reinstating the instruction
pointer
    1.
    发明授权
    System for recovering from a concurrent branch target buffer read with a write allocation by invalidating and then reinstating the instruction pointer 失效
    通过使指令指针无效然后恢复,通过写入分配从并行转移目标缓冲区中恢复的系统

    公开(公告)号:US6154833A

    公开(公告)日:2000-11-28

    申请号:US911141

    申请日:1997-08-11

    IPC分类号: G06F9/38 G06F9/44

    CPC分类号: G06F9/3806 G06F9/3861

    摘要: A circuit and method for handling a hardware conflict experienced by a branch target buffer. The method for handling the hardware conflict includes three steps. First, a determination is made to detect whether there is a write allocation to a branch target buffer (BTB) cache. If so, precedence is given to the write allocation by invalidating at least a first instruction pointer within a BTB pipeline. The first instruction pointer would have been used to read information from the BTB cache for branch prediction, absent the write allocation. Thereafter, the first instruction pointer is recovered by reloading it into the BTB pipeline in order to avoid missing its opportunity to predict. The two cycle delay caused by the invalidation and recovery of the first instruction pointer has little effect on the performance level of the circuit practicing this method of operation.

    摘要翻译: 用于处理分支目标缓冲器所经历的硬件冲突的电路和方法。 处理硬件冲突的方法包括三个步骤。 首先,确定是否存在对分支目标缓冲器(BTB)高速缓存的写入分配。 如果是,则通过使BTB管道中的至少第一指令指针无效来给予写入分配。 第一个指令指针将被用于从BTB缓存读取分支预测的信息,不存在写入分配。 此后,通过将第一个指令指针重新加载到BTB管道中来恢复第一个指令指针,以避免丢失其预测的机会。 由于第一指令指针的无效和恢复引起的两个周期延迟对实现该操作方法的电路的性能水平几乎没有影响。

    Programmable high watermark in stack frame cache using second region as
a storage if first region is full and an event having a predetermined
minimum priority
    2.
    发明授权
    Programmable high watermark in stack frame cache using second region as a storage if first region is full and an event having a predetermined minimum priority 失效
    如果第一区域已满并且具有预定的最小优先级的事件,则使用第二区域作为存储器的堆叠帧高速缓存中的可编程高水印

    公开(公告)号:US5636362A

    公开(公告)日:1997-06-03

    申请号:US314418

    申请日:1994-09-28

    IPC分类号: G06F9/48 G06F12/08 G06F13/00

    摘要: A programmable high watermark for a stack frame cache for eliminating frame spills initiated by certain critical events. A stack frame cache in a microprocessor is divided into two regions. The second region in the stack frame cache is reserved for context switches initiated by high priority events. Low priority events will result in a frame spill when the first region of the stack frame cache is filled. A high priority event will utilize the second region of the stack frame cache for a context switch if the first region is filled, thus eliminating the need for a reference to off-chip main memory.

    摘要翻译: 用于堆栈帧缓存的可编程高水印,用于消除由某些关键事件发起的帧溢出。 微处理器中的堆栈帧高速缓存分为两个区域。 堆栈帧高速缓存中的第二个区域被保留用于由高优先级事件发起的上下文切换。 当堆栈帧缓存的第一个区域被填满时,低优先级事件将导致帧溢出。 如果第一区域被填充,则高优先级事件将利用堆栈帧高速缓存的第二区域进行上下文切换,从而不需要对片外主存储器的引用。