-
1.发明授权Opportunistic transmission of computing system state information within a link based computing system 有权基于链路的计算系统中计算系统状态信息的机会传递公开(公告)号：US07844854B2
公开(公告)日：2010-11-30
申请号：US11174010
申请日：2005-06-30
IPC分类号： G06F11/00
CPC分类号： G06F11/3466 , G06F11/3636 , G06F11/3656
摘要： A method is described that involves within a link based computing system, opportunistically transmitting, into a network utilized by components of the link based computing system, one or more packets that contain computing system state information. The computing system state information includes software state information created through execution of software by said link based computing system. The method also involves collecting the computing system state information at a monitoring and/or debugging system attached to the link based computing system in order to analyze the link based computing system's operation.
摘要翻译： 描述了一种方法，其涉及在基于链路的计算系统内，将由基于链路的计算系统的组件所利用的网络机会地发送到包含计算系统状态信息的一个或多个分组。 计算系统状态信息包括通过由所述基于链路的计算系统执行软件而创建的软件状态信息。 该方法还涉及在连接到基于链路的计算系统的监视和/或调试系统上收集计算系统状态信息，以便分析基于链路的计算系统的操作。
-
2.发明授权Opportunistic transmission of software state information within a link based computing system 失效基于链路的计算系统中的软件状态信息的机会传递公开(公告)号：US07730246B2
公开(公告)日：2010-06-01
申请号：US11173995
申请日：2005-06-30
IPC分类号： G06F13/14
CPC分类号： G06F11/3664
摘要： A method is described that involves determining that software state information of program code is to be made visible to a monitoring system. The method also involves initiating the writing of the software state information into a register. The method also involves waiting for the software state information to be placed onto a link within a link based computing system.
摘要翻译： 描述了一种方法，其涉及确定程序代码的软件状态信息对监视系统可见。 该方法还涉及开始将软件状态信息写入寄存器。 该方法还涉及等待软件状态信息被放置在基于链路的计算系统内的链路上。
-
3.发明授权Electronic system and method for maintaining synchronization of multiple front-end pipelines 失效用于保持多个前端管道同步的电子系统和方法
公开(公告)号：US6044456A
公开(公告)日：2000-03-28
申请号：US002774
申请日：1998-01-05
IPC分类号： G06F9/38
CPC分类号： G06F9/3869
摘要： A system and method are described for maintaining synchronization of information propagating through multiple front-end pipelines operating in parallel. In general, these multiple front-end pipelines become asynchronous in response to a stall condition and re-establish synchronization by flushing both front-end pipelines as well as by selectively releasing these front-end pipelines from their stall condition at different periods of time.
摘要翻译： 描述了一种用于维持通过并行操作的多个前端管道传播的信息的同步的系统和方法。 通常，这些多个前端管道响应于失速状态而变得异步，并且通过冲洗两个前端管道以及通过在不同的时间段内选择性地将这些前端管道从其失速状态中选择性地释放而重新建立同步。
-
4.发明申请Opportunistic Transmission Of Software State Information Within A Link Based Computing System 有权基于链路的计算系统中软件状态信息的机会传递公开(公告)号：US20100241825A1
公开(公告)日：2010-09-23
申请号：US12790383
申请日：2010-05-28
CPC分类号： G06F11/3664
摘要： A method is described that involves determining that software state information of program code is to be made visible to a monitoring system. The method also involves initiating the writing of the software state information into a register. The method also involves waiting for the software state information to be placed onto a link within a link based computing system.
摘要翻译： 描述了一种方法，其涉及确定程序代码的软件状态信息对监视系统可见。 该方法还涉及开始将软件状态信息写入寄存器。 该方法还涉及等待软件状态信息被放置在基于链路的计算系统内的链路上。
-
5.发明授权Opportunistic transmission of software state information within a link based computing system 有权基于链路的计算系统中的软件状态信息的机会传递公开(公告)号：US08122175B2
公开(公告)日：2012-02-21
申请号：US12790383
申请日：2010-05-28
IPC分类号： G06F13/14
CPC分类号： G06F11/3664
摘要： A method is described that involves determining that software state information of program code is to be made visible to a monitoring system. The method also involves initiating the writing of the software state information into a register. The method also involves waiting for the software state information to be placed onto a link within a link based computing system.
摘要翻译： 描述了一种方法，其涉及确定程序代码的软件状态信息对监视系统可见。 该方法还涉及开始将软件状态信息写入寄存器。 该方法还涉及等待软件状态信息被放置在基于链路的计算系统内的链路上。
-
6.发明授权Apparatus and method for detecting and handling self-modifying code conflicts in an instruction fetch pipeline 失效在指令提取流水线中检测和处理自修改代码冲突的装置和方法公开(公告)号：US06405307B1
公开(公告)日：2002-06-11
申请号：US09088634
申请日：1998-06-02
申请人： Keshavram N. Murty , Nazar A. Zaidi
发明人： Keshavram N. Murty , Nazar A. Zaidi
IPC分类号： G06F922
CPC分类号： G06F9/3812 , G06F9/3861 , G06F9/3867
摘要： A system and method are described for detecting and recovering from self-modifying code (SMC) conflicts. In one embodiment, detection is accomplished by accessing the contents of a memory, configured to contain a number of recently executed instructions, to obtain an address. This address is compared to information propagating through a front-end pipeline of an instruction pipeline. The instruction pipeline includes the front-end pipeline to support loading and propagation of information through the instruction pipeline and a back-end pipeline to support execution of instructions along with writeback to the memory. If the address matches the information propagating through the front-end pipeline, a SMC conflict has occurred and at least some of the pipelined information is invalidated.
摘要翻译： 描述了用于从自修改代码（SMC）冲突检测和恢复的系统和方法。 在一个实施例中，通过访问被配置为包含多个最近执行的指令的存储器的内容来获得地址来实现检测。 该地址与通过指令流水线的前端流水线传播的信息进行比较。 指令流水线包括前端流水线，以支持通过指令流水线加载和传播信息，以及后端流水线，以支持执行指令以及向存储器写回。 如果地址匹配通过前端流水线传播的信息，则发生SMC冲突，并且至少部分流水线信息无效。
-
7.发明授权System for recovering from a concurrent branch target buffer read with a write allocation by invalidating and then reinstating the instruction pointer 失效通过使指令指针无效然后恢复，通过写入分配从并行转移目标缓冲区中恢复的系统
公开(公告)号：US6154833A
公开(公告)日：2000-11-28
申请号：US911141
申请日：1997-08-11
CPC分类号： G06F9/3806 , G06F9/3861
摘要： A circuit and method for handling a hardware conflict experienced by a branch target buffer. The method for handling the hardware conflict includes three steps. First, a determination is made to detect whether there is a write allocation to a branch target buffer (BTB) cache. If so, precedence is given to the write allocation by invalidating at least a first instruction pointer within a BTB pipeline. The first instruction pointer would have been used to read information from the BTB cache for branch prediction, absent the write allocation. Thereafter, the first instruction pointer is recovered by reloading it into the BTB pipeline in order to avoid missing its opportunity to predict. The two cycle delay caused by the invalidation and recovery of the first instruction pointer has little effect on the performance level of the circuit practicing this method of operation.
摘要翻译： 用于处理分支目标缓冲器所经历的硬件冲突的电路和方法。 处理硬件冲突的方法包括三个步骤。 首先，确定是否存在对分支目标缓冲器（BTB）高速缓存的写入分配。 如果是，则通过使BTB管道中的至少第一指令指针无效来给予写入分配。 第一个指令指针将被用于从BTB缓存读取分支预测的信息，不存在写入分配。 此后，通过将第一个指令指针重新加载到BTB管道中来恢复第一个指令指针，以避免丢失其预测的机会。 由于第一指令指针的无效和恢复引起的两个周期延迟对实现该操作方法的电路的性能水平几乎没有影响。
-
-
-
-
-
-
搜索结果
7 条记录 (耗时 0.012 秒)
