公开(公告)号：US08138790B1

公开(公告)日：2012-03-20

申请号：US13083889

申请日：2011-04-11

申请人： James Doubler ,  Michael Hammer ,  Jin Zhang

发明人： James Doubler ,  Michael Hammer ,  Jin Zhang

IPC分类号： H03K19/177

CPC分类号： H04J3/0685 ,  H03M9/00 ,  H04J3/0682

摘要： In one embodiment, a programmable logic device (PLD) includes a programmable fabric and hard logic coupled to the programmable fabric. The hard logic includes a timing measurement circuit adapted to measure latency of a data path between first and second points in the programmable logic device, such as the latency of a data path through a link interface configured within the programmable fabric.

摘要翻译： 在一个实施例中，可编程逻辑器件（PLD）包括耦合到可编程结构的可编程结构和硬逻辑。 硬逻辑包括适于测量可编程逻辑设备中的第一和第二点之间的数据路径的等待时间的定时测量电路，诸如通过在可编程结构内配置的链路接口的数据路径的等待时间。

公开(公告)号：US07924054B1

公开(公告)日：2011-04-12

申请号：US12706227

申请日：2010-02-16

申请人： James Doubler ,  Michael Hammer ,  Jin Zhang

发明人： James Doubler ,  Michael Hammer ,  Jin Zhang

IPC分类号： H03K19/177

CPC分类号： H04J3/0685 ,  H03M9/00 ,  H04J3/0682

摘要： A programmable logic device (PLD), is provided that includes: a plurality of SERDES channels; a programmable logic fabric configured to implement an interface for a standardized cellular base station system; wherein the interface receives data words from the SERDES channels and transmits data words to the SERDES channels, and wherein a standard corresponding to the standardized base station system restricts a latency with regard to flow of the data words through the interface, the data words being arranged into frames; and a timing measurement circuit configured to measure a delay between a detection of a first timing point in the frames at first location in the PLD with respect to the interface and a detection of a second timing point in the frames at a second location in the PLD with respect to the interface.

摘要翻译： 提供了一种可编程逻辑器件（PLD），其包括：多个SERDES通道; 被配置为实现标准化蜂窝基站系统的接口的可编程逻辑结构; 其中所述接口接收来自所述SERDES信道的数据字，并向所述SERDES信道发送数据字，并且其中与所述标准化基站系统相对应的标准通过所述接口限制所述数据字流的延迟，所述数据字被布置 成帧; 以及定时测量电路，被配置为测量在PLD中的第一位置处的帧中的第一定时点相对于接口的检测和在PLD中的第二位置处的帧中的第二定时点的检测之间的延迟 相对于界面。