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    Latency measurements for wireless communications
    1.
    发明授权
    Latency measurements for wireless communications 有权
    无线通信的延迟测量

    公开(公告)号：US08138790B1

    公开(公告)日：2012-03-20

    申请号：US13083889

    申请日：2011-04-11

    申请人： James Doubler ,  Michael Hammer ,  Jin Zhang

    发明人： James Doubler ,  Michael Hammer ,  Jin Zhang

    IPC分类号： H03K19/177

    CPC分类号： H04J3/0685 ,  H03M9/00 ,  H04J3/0682

    摘要： In one embodiment, a programmable logic device (PLD) includes a programmable fabric and hard logic coupled to the programmable fabric. The hard logic includes a timing measurement circuit adapted to measure latency of a data path between first and second points in the programmable logic device, such as the latency of a data path through a link interface configured within the programmable fabric.

    摘要翻译： 在一个实施例中，可编程逻辑器件（PLD）包括耦合到可编程结构的可编程结构和硬逻辑。 硬逻辑包括适于测量可编程逻辑设备中的第一和第二点之间的数据路径的等待时间的定时测量电路，诸如通过在可编程结构内配置的链路接口的数据路径的等待时间。

    Latency measurements for wireless communications
    2.
    发明授权
    Latency measurements for wireless communications 有权
    无线通信的延迟测量

    公开(公告)号：US07924054B1

    公开(公告)日：2011-04-12

    申请号：US12706227

    申请日：2010-02-16

    申请人： James Doubler ,  Michael Hammer ,  Jin Zhang

    发明人： James Doubler ,  Michael Hammer ,  Jin Zhang

    IPC分类号： H03K19/177

    CPC分类号： H04J3/0685 ,  H03M9/00 ,  H04J3/0682

    摘要： A programmable logic device (PLD), is provided that includes: a plurality of SERDES channels; a programmable logic fabric configured to implement an interface for a standardized cellular base station system; wherein the interface receives data words from the SERDES channels and transmits data words to the SERDES channels, and wherein a standard corresponding to the standardized base station system restricts a latency with regard to flow of the data words through the interface, the data words being arranged into frames; and a timing measurement circuit configured to measure a delay between a detection of a first timing point in the frames at first location in the PLD with respect to the interface and a detection of a second timing point in the frames at a second location in the PLD with respect to the interface.

    摘要翻译： 提供了一种可编程逻辑器件（PLD），其包括：多个SERDES通道; 被配置为实现标准化蜂窝基站系统的接口的可编程逻辑结构; 其中所述接口接收来自所述SERDES信道的数据字，并向所述SERDES信道发送数据字，并且其中与所述标准化基站系统相对应的标准通过所述接口限制所述数据字流的延迟，所述数据字被布置 成帧; 以及定时测量电路，被配置为测量在PLD中的第一位置处的帧中的第一定时点相对于接口的检测和在PLD中的第二位置处的帧中的第二定时点的检测之间的延迟 相对于界面。

    In-system reconfigurable circuit for mapping data words of different lengths
    3.
    发明授权
    In-system reconfigurable circuit for mapping data words of different lengths 有权
    用于映射不同长度的数据字的系统内可重构电路

    公开(公告)号：US08823561B1

    公开(公告)日：2014-09-02

    申请号：US13452060

    申请日：2012-04-20

    申请人： Michael Hammer ,  David Pierce ,  Jin Zhang

    发明人： Michael Hammer ,  David Pierce ,  Jin Zhang

    IPC分类号： H03M7/40

    CPC分类号： H04J3/1605 ,  H04J3/047 ,  H04W28/065 ,  H04W88/085

    摘要： A de-mapping circuit for de-mapping input words of a first length into output words of a second length different from the first length. In one embodiment, the circuit includes a word register of the first length and temporary registers of the second length. The word register successively stores each of the inputs words in response to cycles of a clock. The temporary registers temporarily store the output words. Multiplexers configured by address signals select bits from stored input words and store the selected bits into the temporary registers to form temporarily stored output words.

    摘要翻译： 一种用于将第一长度的输入字解映射成与第一长度不同的第二长度的输出字的去映射电路。 在一个实施例中，电路包括第一长度的字寄存器和第二长度的临时寄存器。 字寄存器响应于时钟的周期而连续地存储每个输入字。 临时寄存器临时存储输出字。 由地址信号配置的多路复用器从存储的输入字中选择位，并将所选位存储到临时寄存器中以形成临时存储的输出字。

    In-system reconfigurable circuit for mapping data words of different lengths
    4.
    发明授权
    In-system reconfigurable circuit for mapping data words of different lengths 有权
    用于映射不同长度的数据字的系统内可重构电路

    公开(公告)号：US08165164B1

    公开(公告)日：2012-04-24

    申请号：US12494822

    申请日：2009-06-30

    申请人： Michael Hammer ,  David Pierce ,  Jin Zhang

    发明人： Michael Hammer ,  David Pierce ,  Jin Zhang

    IPC分类号： H04J3/24

    CPC分类号： H04J3/1605 ,  H04J3/047 ,  H04W28/065 ,  H04W88/085

    摘要： A mapping circuit is provided for mapping first data words into frames of second data words, wherein the first and second data words are of different length. In addition, a de-mapping circuit is provided for de-mapping the frames of second data words into the first data words. The mapping and de-mapping is responsive to address signals that may be stored in a memory such that a desired mapping or de-mapping corresponds to a particular programming of the memory. In this fashion, the mapping and de-mapping is in-system reconfigurable.

    摘要翻译： 提供映射电路用于将第一数据字映射到第二数据字的帧，其中第一和第二数据字的长度不同。 另外，提供去映射电路用于将第二数据字的帧解映射成第一数据字。 映射和解映射响应于可存储在存储器中的地址信号，使得期望的映射或解映射对应于存储器的特定编程。 以这种方式，映射和映射是系统内可重新配置的。

    Alignment circuit for parallel data streams
    5.
    发明授权
    Alignment circuit for parallel data streams 有权
    并行数据流对齐电路

    公开(公告)号：US08495264B1

    公开(公告)日：2013-07-23

    申请号：US13178536

    申请日：2011-07-08

    申请人： Michael Hammer ,  Jin Zhang

    发明人： Michael Hammer ,  Jin Zhang

    IPC分类号： G06F13/12 ,  H04L7/00

    CPC分类号： G06F13/12 ,  G06F13/4009 ,  G09G2370/10 ,  H04L7/00

    摘要： Parallel data generated by demultiplexing received serial data such as in a Serial RapidIO (SRIO) data stream can become misaligned as a result of, e.g., clock tolerance compensation (CTC) processing at the receiver. In one embodiment of the invention, the misaligned parallel data is properly aligned based on a mapping from each of a finite number of possible previous alignment conditions (e.g., words A-D) to a corresponding finite number of possible subsequent alignment conditions (e.g., words B-G). The change from a previous alignment condition to a different subsequent alignment condition is recognized by determining the location of start-of-packet (SOP) or start-of-control-symbol (SOC) data in the parallel data stream.

    摘要翻译： 通过解复用接收到的串行数据（例如串行RapidIO（SRIO）数据流）中产生的并行数据可能会因接收机的时钟容差补偿（CTC）处理而变得不对齐。 在本发明的一个实施例中，基于从有限数量的可能的先前对准条件（例如，字AD）到对应的有限数量的可能的后续对准条件（例如，字BG ）。 通过确定并行数据流中的分组数据包（SOP）或控制开始符号（SOC）数据的位置，可以识别从先前对准条件到不同的后续对准条件的变化。

    Multi-axial connection system
    6.
    发明授权
    Multi-axial connection system 有权
    多轴连接系统

    公开(公告)号：US08951290B2

    公开(公告)日：2015-02-10

    申请号：US12577503

    申请日：2009-10-12

    申请人： Michael Hammer ,  Stephen Termyna

    发明人： Michael Hammer ,  Stephen Termyna

    IPC分类号： A61B17/70 ,  A61B17/86

    CPC分类号： A61B17/7002 ,  A61B17/7032 ,  A61B17/7034 ,  A61B17/7035 ,  A61B17/7037 ,  A61B17/7041 ,  A61B17/8605 ,  A61B17/8635 ,  A61B17/864 ,  A61B2017/8655

    摘要： A system and method for a multi-axial connection of an apparatus to bone. The system may include a fastener inserted into a body and a head of the fastener held within a chamber of the body through a combination of a retention ring, a pressure cap, a rod, and a compression element. The compression element applies force to the rod which, in turn, pushed on the pressure cap. The force on the pressure cap urges it against the head of the fastener and pushed it against the retention ring. The force on the retention ring causes it to expand to the walls of the chamber. Once the ring can no longer expand within the chamber, the head of the fastener is wedged between the retention ring and the pressure cap.

    摘要翻译： 一种用于设备与骨骼的多轴连接的系统和方法。 该系统可以包括通过保持环，压力盖，杆和压缩元件的组合件插入到主体中的紧固件和固定在身体的室内的紧固件的头部。 压缩元件对杆施加力，该杆又被压在压力盖上。 压力盖上的力将其推向紧固件的头部并将其推向保持环上。 保持环上的力使其膨胀到室的壁。 一旦环在腔室内不再膨胀，紧固件的头部楔入保持环和压力盖之间。

    Correlator having user-defined processing
    7.
    发明授权
    Correlator having user-defined processing 有权
    相关器具有用户定义的处理

    公开(公告)号：US07606851B2

    公开(公告)日：2009-10-20

    申请号：US11202149

    申请日：2005-08-10

    申请人： David Pierce ,  Michael Hammer

    发明人： David Pierce ,  Michael Hammer

    IPC分类号： G06F17/15

    CPC分类号： G06F17/15

    摘要： In one embodiment of the invention, a circuit may include and/or involve a correlator, a programmable fabric, and logic to enable selection of one of default processing logic and alternate processing logic to process corresponding data and coefficient values of the correlator.

    摘要翻译： 在本发明的一个实施例中，电路可以包括和/或涉及相关器，可编程结构和逻辑，以使得能够选择默认处理逻辑和备用处理逻辑之一来处理相关器的对应数据和系数值。

    Correlator having user-defined processing
    10.
    发明申请
    Correlator having user-defined processing 有权
    相关器具有用户定义的处理

    公开(公告)号：US20070038692A1

    公开(公告)日：2007-02-15

    申请号：US11202149

    申请日：2005-08-10

    申请人： David Pierce ,  Michael Hammer

    发明人： David Pierce ,  Michael Hammer

    IPC分类号： G06F17/15

    CPC分类号： G06F17/15

    摘要： In one embodiment of the invention, a circuit may include and/or involve a correlator, a programmable fabric, and logic to enable selection of one of default processing logic and alternate processing logic to process corresponding data and coefficient values of the correlator.

    摘要翻译： 在本发明的一个实施例中，电路可以包括和/或涉及相关器，可编程结构和逻辑，以使得能够选择默认处理逻辑和备用处理逻辑之一来处理相关器的对应数据和系数值。