公开(公告)号：US4620278A

公开(公告)日：1986-10-28

申请号：US527063

申请日：1983-08-29

申请人： James G. Ellsworth ,  Thomas E. Wulling

发明人： James G. Ellsworth ,  Thomas E. Wulling

IPC分类号： G06F13/378 ,  G06F13/36

CPC分类号： G06F13/378

摘要： A digital communication bus upon which arbitration is distributed in a multiplicity of communicable interconnected bus interface logics supports unique signals to each associated on user device and upon the bus. Arbitration inhibiting signals, called inhibit request signals, allow any one(s) user device(s) to inhibit the new entrance, via requests, into arbitration of all other bus interconnected bus interface logics and associated user devices. Arbitration among bus interface logics already registering requests continues in priority order. Each user device may, via a signal called retract request, deregister, or cancel, requests previously registered at the associated bus interface logics to arbitrate for ownership of the bus. Each user device may, via a signal called stop bus, cause continuous interface logics while being precluded from recognition that arbitration should ever be won. When the highest priority one user device so exercises the signal stop bus, then its associated bus interface logics always wins arbitrated ownership of the bus, but naught is known by, or done with, any user device of such ownership; effectively meaning the bus is stopped of normal data communication. Any bus-owning user device may communicate a signal, called priority disable, to the associated bus interface logic and upon a dedicated line of the bus, which signal, called priority disable, to the associated bus interface logic and upon a dedicated line of the bus, which signal postpones the recognition of the winning of arbitration in order that the current bus-owning user may longer retain ownership. Any particular bus interface logics may be, responsively to the setting of a flip-flop called the bus enable flip-flop by any external agency such as any User device or maintenance processor, disabled of any bus activity whatsoever, locking out the associated user device.

公开(公告)号：US4511967A

公开(公告)日：1985-04-16

申请号：US466761

申请日：1983-02-15

申请人： Jerome J. Witalka ,  Howard L. Buettner ,  James G. Ellsworth

发明人： Jerome J. Witalka ,  Howard L. Buettner ,  James G. Ellsworth

IPC分类号： G01R31/3185 ,  G06F11/273 ,  G06F1/00

CPC分类号： G01R31/318547 ,  G01R31/318566 ,  G06F11/2294

摘要： The loading (writing) of plural successive data strings of specifiable bit-length and numbers to a scan/set testable register (called a CONTROL STORE SCAN LOOP STRING) from which it may then be transferred to a control store (called a CONTROL STORE (RAM)) both within a remote slave digital logic device (called a CENTRAL COMPLEX) is bit-serially conducted upon one signal line of a scan/set network by a controlling digital logic device (called a SUPPORT PROCESSOR) in substantially simultaneous time to the reading of the previous contents of such register (and control store) bit-serially via another signal line of said scan/set network. Both signal lines and devices together form a circular BIT-SERIAL SCAN LOOP, upon which the bit-serial writing and reading is time overlapped. The data strings read are the echo-back of the data strings previously written, and are, in a first operational mode called ECHO, lodged in a buffer memory (called a SCAN/SET BUFFER) of the controlling digital logic device wherein, subsequent to communication, they may be programmably compared with the data strings written in verification of process integrity. In a selectable alternative second operational mode called VERIFY, each successive data string read back is, in substantially simultaneous time, automatically compared with the data string as previously written. Thusly, loading (writing) and reading and verifying activities on variably specifiable numbers of data strings of variably specifiable bit-length communicated upon a BIT-SERIAL SCAN LOOP all transpire substantially concurrently in simultaneous time.

摘要翻译： 将可指定位长和数字的多个连续数据串加载（写入）到扫描/设置可测试寄存器（称为控制存储扫描循环字符串），然后将其从传输到控制存储器（称为CON​​TROL STORE RAM））在远程从属数字逻辑器件（称为CENTRAL COMPLEX）中，通过控制数字逻辑器件（称为支持处理器）在扫描/设置网络的一个信号线上进行位串行传输 通过所述扫描/设置网络的另一个信号线来顺序读取这种寄存器（和控制存储器）的先前内容。 两个信号线和器件一起形成一个圆形的BIT串行扫描环，位串行写入和读取时间重叠。 读取的数据串是先前写入的数据串的回波，并且被称为ECHO的第一操作模式存储在控制数字逻辑器件的缓冲存储器（称为SCAN / SET BUFFER）中，其中，在 通信，它们可以可编程地与在验证过程完整性中编写的数据串进行比较。 在称为VERIFY的可选择的备选的第二操作模式中，读取的每个连续的数据串在大致同时的时间内与先前写过的数据串自动地进行比较。 因此，在双向串行扫描环路上通信的可变指定位长度的可变指定数量的数据串的加载（写入）和读取和验证活动全部同时在同时发生。