公开(公告)号：US06728845B2

公开(公告)日：2004-04-27

申请号：US10208264

申请日：2002-07-30

Applicant: Matthew J. Adiletta ,  William Wheeler ,  James Redfield ,  Daniel Cutter ,  Gilbert Wolrich

Inventor： Matthew J. Adiletta ,  William Wheeler ,  James Redfield ,  Daniel Cutter ,  Gilbert Wolrich

IPC: G06F1300

CPC classification number: G06F13/1642

Abstract: A controller for a random access memory (RAM), such as a static ram (SRAM), includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues. The memory controller may be used in parallel processing systems and may also include an order queue, a lock lookup content addressable memory (CAM) and a read lock fail queue. A system including a media access controller (MAC), a network processor and an SRAM controller, and a method for controlling a RAM, are also described.

Abstract translation: 用于诸如静态RAM（SRAM）的随机存取存储器（RAM）的控制器包括保存来自多个微控制器功能单元的存储器引用的地址和命令队列。 地址和命令队列包括存储读取存储器引用的读取队列。 控制器还包括第一读/写队列，其保存来自核心处理器的存储器引用和控制逻辑，所述控制逻辑包括检测每个队列的完整性的仲裁器以及尚未完成的存储器引用的完成状态以从以下之一中选择存储器引用 排队。 存储器控制器可以在并行处理系统中使用，并且还可以包括订单队列，锁定查找内容可寻址存储器（CAM）和读锁定失败队列。 还描述了包括媒体访问控制器（MAC），网络处理器和SRAM控制器的系统以及用于控制RAM的方法。

公开(公告)号：US07305500B2

公开(公告)日：2007-12-04

申请号：US10776702

申请日：2004-02-10

Applicant: Matthew J. Adiletta ,  William Wheeler ,  James Redfield ,  Daniel Cutter ,  Gilbert Wolrich

Inventor： Matthew J. Adiletta ,  William Wheeler ,  James Redfield ,  Daniel Cutter ,  Gilbert Wolrich

IPC: G06F9/46

CPC classification number: G06F13/1642

Abstract: A controller for a random access memory includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.

Abstract translation: 用于随机存取存储器的控制器包括保存来自多个微控制器功能单元的存储器引用的地址和命令队列。 地址和命令队列包括存储读取存储器引用的读取队列。 控制器还包括第一读/写队列，其保存来自核心处理器的存储器引用和控制逻辑，所述控制逻辑包括检测每个队列的完整性的仲裁器以及尚未完成的存储器引用的完成状态以从以下之一中选择存储器引用 排队。

公开(公告)号：US5418321A

公开(公告)日：1995-05-23

申请号：US991059

申请日：1992-12-15

Applicant: Glenn J. Keller ,  Timothy J. McDonald ,  James Redfield ,  Robert S. Schmid

Inventor： Glenn J. Keller ,  Timothy J. McDonald ,  James Redfield ,  Robert S. Schmid

IPC: G10H7/00

CPC classification number: G10H7/002

Abstract: An audio channel system provides an analog signal corresponding to a sound waveform in a computer system. The audio channel system includes a plurality of audio channels. Each audio channel contains a predetermined number of audio data samples for producing a particular sound waveform. A plurality of volume bits define a volume level of each audio data sample to be played. An audio processor processes the sound waveforms of each audio channel. The audio processor acts as a shared processing element which receives the audio data samples from each audio channel. The audio processor divides the audio data samples into a plurality of data such that the plurality of data for each audio data sample is pipelined through the audio processor in a serial manner. The plurality of data for each audio data sample for each audio channel is in various processing stages at any given time. The audio processor combines the data samples and volume bits to produce an audio output signal for each audio channel to produce a total audio output signal.

Abstract translation: 音频通道系统提供对应于计算机系统中的声音波形的模拟信号。 音频通道系统包括多个音频通道。 每个音频通道包含用于产生特定声音波形的预定数量的音频数据样本。 多个音量位定义要播放的每个音频数据样本的音量级别。 音频处理器处理每个音频通道的声音波形。 音频处理器用作从每个音频通道接收音频数据样本的共享处理元件。 音频处理器将音频数据样本分成多个数据，使得每个音频数据样本的多个数据以串行方式通过音频处理器流水线化。 用于每个音频信道的每个音频数据样本的多个数据在任何给定时间处于各种处理阶段。 音频处理器组合数据采样和音量位以产生用于每个音频通道的音频输出信号以产生总音频输出信号。

公开(公告)号：US06427196B1

公开(公告)日：2002-07-30

申请号：US09387110

申请日：1999-08-31

Applicant: Matthew J. Adiletta ,  William Wheeler ,  James Redfield ,  Daniel Cutter ,  Gilbert Wolrich

Inventor： Matthew J. Adiletta ,  William Wheeler ,  James Redfield ,  Daniel Cutter ,  Gilbert Wolrich

IPC: G06F1300

CPC classification number: G06F13/1642

Abstract: A controller for a random access memory includes an address and command queue that holds memory references from a plurality of micro control functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.

Abstract translation: 用于随机存取存储器的控制器包括保存来自多个微控制功能单元的存储器引用的地址和命令队列。 地址和命令队列包括存储读取存储器引用的读取队列。 控制器还包括第一读/写队列，其保存来自核心处理器的存储器引用和控制逻辑，所述控制逻辑包括检测每个队列的完整性的仲裁器以及尚未完成的存储器引用的完成状态以从以下之一中选择存储器引用 排队。