公开(公告)号：US20130341518A1

公开(公告)日：2013-12-26

申请号：US13529532

申请日：2012-06-21

Applicant: Mark David Fries ,  James Widen ,  Paul Holtermann

Inventor： Mark David Fries ,  James Widen ,  Paul Holtermann

IPC: H03M1/50 ,  G01T1/164 ,  H01L27/146

CPC classification number: A61B6/037 ,  A61B6/4258 ,  A61B6/5205

Abstract: A timing circuit that includes a first serializer/deserializer (SERDES) configured to receive a parallel rate clock signal and a system clock start signal from an imaging system and generate a first output, a second SERDES configured to receive a stop signal that is based on an output from the medical imaging system and generate a second output, and a timestamp calculator configured to utilize the first and second outputs to generate a timestamp. A medical imaging system and a method of operating a timing circuit are also described.

Abstract translation: 一种定时电路，包括被配置为从成像系统接收并行速率时钟信号和系统时钟启动信号并产生第一输出的第一串行器/解串行器（SERDES），第二SERDES被配置为接收基于 来自医学成像系统的输出并产生第二输出，以及时间戳计算器，被配置为利用第一和第二输出来产生时间戳。 还描述了医疗成像系统和操作定时电路的方法。

公开(公告)号：US08822933B2

公开(公告)日：2014-09-02

申请号：US13529532

申请日：2012-06-21

Applicant: Mark David Fries ,  James Widen ,  Paul Holtermann

Inventor： Mark David Fries ,  James Widen ,  Paul Holtermann

IPC: G01T1/164

CPC classification number: A61B6/037 ,  A61B6/4258 ,  A61B6/5205

Abstract: A timing circuit that includes a first serializer/deserializer (SERDES) configured to receive a parallel rate clock signal and a system clock start signal from an imaging system and generate a first output, a second SERDES configured to receive a stop signal that is based on an output from the medical imaging system and generate a second output, and a timestamp calculator configured to utilize the first and second outputs to generate a timestamp. A medical imaging system and a method of operating a timing circuit are also described.

Abstract translation: 一种定时电路，包括被配置为从成像系统接收并行速率时钟信号和系统时钟启动信号并产生第一输出的第一串行器/解串行器（SERDES），第二SERDES被配置为接收基于 来自医学成像系统的输出并产生第二输出，以及时间戳计算器，被配置为利用第一和第二输出来产生时间戳。 还描述了医疗成像系统和操作定时电路的方法。