公开(公告)号：US12204287B2

公开(公告)日：2025-01-21

申请号：US17816894

申请日：2022-08-02

Applicant: Apple Inc.

Inventor： Bo Zhao ,  Joao Pedro da Silva Cerqueira ,  Pangjie Xu ,  Steven Lu

IPC: H03M1/50 ,  G01R19/255 ,  G04F10/00 ,  H03M1/08

Abstract: A multi-chain measurement circuit is disclosed. The measurement circuit includes first and second chains of serially-connected buffer circuits coupled in parallel, each of which propagates an input signal. A set of storage circuits is configured to store logic values generated by the first and second sets of buffer circuits in response to the transitioning of a clock signal. The logic values stored in the storage circuits result in a digital value indicative of a total number of serially-connected storage circuits through which the input signal has propagated at the time of the transition of the operating clock signal.

公开(公告)号：US20250015813A1

公开(公告)日：2025-01-09

申请号：US18763552

申请日：2024-07-03

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives

Inventor： Ali MOSTAFA ,  Franck BADETS ,  Emmanuel HARDY

IPC: H03M1/50 ,  H03K19/20

Abstract: The invention concerns a programmable voltage to time converter, comprising: a locking frequency generator configured to generate a locking frequency; a current generator configured to generate a biasing current; a relaxation oscillator configured to be powered by the biasing current and to generate an output voltage signal from the locking frequency, a gain control word and an input voltage signal; a phase difference block configured to determine a phase difference between a first signal corresponding to the output voltage signal and a second signal determined based on the locking frequency. The relaxation oscillator comprises a component presenting a linearly controllable characteristic. The voltage to time converter presents a gain linearly or dB-linearly controllable based on the gain control word by controlling linearly said characteristic of said component.

公开(公告)号：US20240429936A1

公开(公告)日：2024-12-26

申请号：US18341237

申请日：2023-06-26

Applicant: CHENJUN HSU

Inventor： CHENJUN HSU

IPC: H03M1/50 ,  H03M1/08 ,  H03M1/12

Abstract: The present application provides an all-digital multi-phase DC-DC controller. The digital DC-DC controller includes time-based analog-to-digital converters (ADCs) for converting analog voltage signals into digital-domain signals so as to benefit from gate length scaling without limited by the low voltage swing. Also, the DC-DC controller further includes a digital control circuit and a time-based modulator. The digital control circuit can control the time-based modulator in a digital domain, thereby reducing the affection caused by process, voltage and temperature (PVT) variation. Also, the time-based modulator can adjust the timing of the PWM signals and avoid the performance degradation caused by circuit mismatch. Since the digital control circuit can be fully synthesizable, it allows implementations in all kinds of digital CMOS processes with a small chip area.

公开(公告)号：US12028069B2

公开(公告)日：2024-07-02

申请号：US17742112

申请日：2022-05-11

Applicant: Kratos SRE, Inc.

Inventor： Seth D. Cohen

IPC: H03K3/017 ,  H03K3/037 ,  H03K19/177 ,  H03K19/20 ,  H03M1/50 ,  H03M7/00

CPC classification number: H03K3/017 ,  H03K3/037 ,  H03K19/177 ,  H03K19/20 ,  H03M1/504 ,  H03M7/00

Abstract: Technologies are provided for generation of programmable pulse signals using inverse chaotic maps, without reliance on a clocking signal. Some embodiments of the technologies include an apparatus that can receive a sequence of bits having a defined number of bits, where the sequence of bits represent a desired continuous pulse signal having a programmable width in time-domain. The apparatus can also can receive a precursor continuous pulse signal having an arbitrary width in time-domain that fits within the dynamic range of the apparatus. The apparatus can generate the desired continuous pulse signal by transforming the precursor continuous pulse signal using the sequence of bits and an inverse chaotic map.

公开(公告)号：US11984908B2

公开(公告)日：2024-05-14

申请号：US17298449

申请日：2019-11-27

Applicant: Microvision, Inc.

Inventor： Ralf Beuschel

IPC: H03M1/50 ,  G01S7/484 ,  G01S7/4865 ,  H03M1/56 ,  G01S17/931

CPC classification number: H03M1/56 ,  G01S7/484 ,  G01S7/4866 ,  G01S17/931

Abstract: Described herein are analog-to-digital converters (ADCs) that utilize time-to-digital converters (TDCs) and a histogram block to generate time-correlated histograms from analog signals. In some implementations, the time-to-digital converters determine time intervals for which the analog signal above or below a ramp signal, and the histogram block generates the time-correlated histograms of values using the determined time intervals. Furthermore, in some implementations, the analog-to-digital converters receive the analog signals from photodiodes, such as photo diodes used in Light Detection and Ranging (LIDAR) devices. In some such applications, the use of time intervals to generate time-correlated histograms may be used to reduce the effects of time jitter.

公开(公告)号：US11936398B2

公开(公告)日：2024-03-19

申请号：US17041630

申请日：2019-03-26

Applicant: KONINKLIJKE PHILIPS N.V.

Inventor： Sotir Filipov Ouzounov ,  Emil Dimitrov Totev

IPC: H03M1/16 ,  G01S7/52 ,  G04F10/00 ,  H03M1/50 ,  H03M3/00 ,  H04B11/00

CPC classification number: H03M1/164 ,  G01S7/52023 ,  G04F10/005 ,  H03M1/50 ,  H04B11/00 ,  H03M3/30

Abstract: The invention provides a signal processing system, for transferring analog signals from a probe to a remote processing unit. The system comprises a first ASIC at a probe, which is adapted to receive an analog probe signal. The first ASIC comprises an asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator is adapted to: receive the analog probe signal; and output a binary bit-stream. The system further comprises a second ASIC at the remote processing unit, adapted to receive the binary bit-stream. The asynchronous may further include a time gain function circuit, the first ASIC may further comprise a multiplexer, the second ASIC may further comprise a time-to-digital converter. The time to digital converter may be a pipelined time-to-digital converter.

公开(公告)号：US20230308112A1

公开(公告)日：2023-09-28

申请号：US17704511

申请日：2022-03-25

Applicant: Cypress Semiconductor Corporation

Inventor： Avri HARUSH

IPC: H03M3/00 ,  H03M1/50 ,  G04F10/00 ,  H03L7/099

CPC classification number: H03M3/424 ,  H03M1/502 ,  G04F10/005 ,  H03L7/0991

Abstract: A digitally-controlled oscillator (DCO) circuit includes a digital-to-analog converter (DAC) to generate a first current based on most significant bits of a multi-bit code received from a time-to-digital converter (TDC) of a digital phase-locked loop (PLL). The DCO circuit further includes a sigma-delta modulator (SDM) to modulate least significant bits of the multi-bit code into a set of digital bits based on a first frequency of a feedback clock of the DPLL. The set of digital bits is to cause the DAC to generate a second current. The DCO circuit further includes a ring oscillator coupled to the DAC, the ring oscillator to generate an alternating-current (AC) output signal having a second frequency corresponding to a combination of the first current and the second current.

公开(公告)号：US11742872B2

公开(公告)日：2023-08-29

申请号：US17728985

申请日：2022-04-26

Applicant: Asahi Kasei Microdevices Corporation

Inventor： Eizo Ichihara ,  Shintaro Kawazoe

IPC: H03M1/12 ,  H03M1/36 ,  H03M3/00 ,  H03M1/50 ,  H03M1/08

CPC classification number: H03M1/1245 ,  H03M1/0854 ,  H03M1/361 ,  H03M1/50 ,  H03M3/39

Abstract: Provided is an AD converter, including: an analog signal input circuit, configured to be input with an analog input signal, and output a first analog output signal based on the analog input signal and a second analog output signal based on the analog input signal at different timing; an integral circuit, configured to integrate the first analog output signal and the second analog output signal and output the first integral signal and the second integral signal; a predictive circuit, configured to predict an integral signal output after the output by the integral circuit based on the first integral signal and the second integral signal output by the integral circuit, and output a predictive integral signal; and a quantization circuit, configured to generate a digital signal with the predictive integral signal quantized.

公开(公告)号：US20230170800A1

公开(公告)日：2023-06-01

申请号：US17994134

申请日：2022-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Huidong Gwon ,  Byongdeok Choi ,  Taehwang Kong ,  Junhyeok Yang ,  Junhwan Jang

IPC: H02M3/157 ,  H03M1/44 ,  H03M1/50 ,  H03M1/06

CPC classification number: H02M3/157 ,  H03M1/44 ,  H03M1/502 ,  H03M1/0607

Abstract: An LDO regulator includes a voltage-to-time converter configured to convert a fluctuation in an output voltage sensed from an output node into a time domain signal having a pulse type, and output the time domain signal, based on a clock signal; a time-to-voltage converter configured to receive the time domain signal, convert the time domain signal into a first voltage control signal performing first compensation for the output voltage, and output the first voltage control signal; an analog amplifier configured to output a second voltage control signal continuously performing second compensation for the output voltage, regardless of the clock signal; and a first pass transistor configured to drive the output voltage based on the second voltage control signal. The LDO regulator is configured to reduce the fluctuation in the output voltage, based on the first compensation and the second compensation.

公开(公告)号：US20230087101A1

公开(公告)日：2023-03-23

申请号：US17886033

申请日：2022-08-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoichi IIZUKA ,  Fukashi MORISHITA

IPC: H03M1/36 ,  H03K23/54 ,  H03M1/08 ,  H03M1/50 ,  H03K23/44

Abstract: An integrating Analog-to-digital converter has a global counter that outputs a counter code signal including a multiphase signal. It also has a column circuit including: a ramp wave generation circuit outputting a ramp wave voltage; a comparator comparing the ramp wave voltage with a pixel voltage; and a latch circuit latching the counter code signal at output inversion timing of the comparator. An output value of the latch circuit is used as a digital conversion output value per the column circuit. The counter has a phase division circuit outputting, as an LSB of the digital conversion output value of the integrating analog-to-digital converter, a phase division signal to the latch circuit, the phase division signal dividing a phase of the counter code signal. The phase division circuit is arranged to a plurality of column circuits, and the LSB is shared by a plurality of phase division circuits.