公开(公告)号：US4893116A

公开(公告)日：1990-01-09

申请号：US120902

申请日：1987-11-16

申请人： David L. Henderson ,  Brian K. Herbert ,  Michael D. Lahey ,  Jamey L. Robbins

发明人： David L. Henderson ,  Brian K. Herbert ,  Michael D. Lahey ,  Jamey L. Robbins

IPC分类号： G09G1/28 ,  G09G5/02 ,  G09G5/36

CPC分类号： G09G5/022

摘要： An interface controller, situated between a graphics controller and a memory array in a color video display system operable in a read-modify-write mode, configured to detect a select transparency color in whole or in part and to respond by selectively changing the color binary data for the corresponding pixel in a frame buffer. In another aspect, the invention includes drawing modes impelmented by logically combining pixel color binary data in accordance with a defined truth table so as to allow the pixel color data representing a new image to interact in a defined manner based upon color with the data in a previously defined image. As implemented, the binary data in the frame buffer is acted upon in a read-modify-write sequence whereby the various logic operations analyze the source (foreground) pixel data, the destination (background) pixel data, in the context of control signals, to define the pixel color data written into the frame buffer as the color representation for that pixel position.

摘要翻译： 位于彩色视频显示系统中的图形控制器和存储器阵列之间的接口控制器，其以读 - 修改 - 写模式操作，被配置为全部或部分地检测选择透明度颜色，并通过选择性地改变颜色二进制 帧缓冲器中相应像素的数据。 在另一方面，本发明包括通过根据定义的真值表逻辑地组合像素颜色二进制数据来驱动的绘制模式，以便允许表示新图像的像素颜色数据以定义的方式基于颜色与数据在 先前定义的图像。 如实现的，帧缓冲器中的二进制数据以读 - 修改 - 写序列的方式被执行，由此各种逻辑运算在控制信号的上下文中分析源（前景）像素数据，目的地（背景）像素数据， 将写入帧缓冲器的像素颜色数据定义为该像素位置的颜色表示。

公开(公告)号：US5146211A

公开(公告)日：1992-09-08

申请号：US566014

申请日：1990-08-10

申请人： John M. Adams ,  Brian K. Herbert ,  Stephen M. Johnson ,  Jamey L. Robbins

发明人： John M. Adams ,  Brian K. Herbert ,  Stephen M. Johnson ,  Jamey L. Robbins

IPC分类号： G09G5/08

CPC分类号： G09G5/08

摘要： An architecture for generating a hardware cursor in the context of a bit mapped video display system operable from a frame buffer with non-displayed but addressable memory space. A segment of the non-displayed memory is loaded with cursor information controlling the generation of its outline and its color pattern. When accessed, this cursor control data is accessed from the non-displayed segment of the memory during each horizontal blank time preceding the raster scan of the video pattern data subject to cursor overlay. Location of the cursor within the video display is determined by a group of position registers which are loaded by the CPU with cursor position data during the vertical blank time. The position registers in conjunction with a group of counters coordinate the insertion of the cursor data into a byte stream of display data as it makes its way to the CRT screen. This display data is stored in the frame buffer and is transferred to the pixel output buffer. The display data in the pixel output buffer is subsequently interpreted into colors and intensities, and displayed on the CRT screen using known techniques. The vertical and horizontal locations of the cursor are synchronously incremented on a pixel by pixel basis during the scan of a frame buffer line. At the appropriate location, cursor data is multiplexed and/or logically combined with the bit stream of frame buffer data to overlay the cursor characteristics upon the video display data. The cursor data buffer can thereby be relatively small yet overlay a relatively large cursor with minimal manipulation by the computer controlling the video display.

摘要翻译： 一种用于在从具有非显示但可寻址的存储器空间的帧缓冲器中操作的位映射视频显示系统的上下文中生成硬件光标的架构。 未显示的存储器的段被加载有控制其轮廓及其颜色模式的生成的光标信息。 当访问时，在光标覆盖的视频图案数据的光栅扫描之前的每个水平空白时间期间，从存储器的未显示段访问该光标控制数据。 视频显示中的光标的位置由在垂直空白时间期间由CPU加载光标位置数据的一组位置寄存器确定。 位置寄存器结合一组计数器协调将光标数据插入到显示数据的字节流中，当它进入CRT屏幕时。 该显示数据被存储在帧缓冲器中并被传送到像素输出缓冲器。 像素输出缓冲器中的显示数据随后被解释为颜色和强度，并使用已知技术在CRT屏幕上显示。 在帧缓冲线的扫描期间，光标的垂直和水平位置在逐个像素的基础上同步递增。 在适当的位置，光标数据被多路复用和/或逻辑地与帧缓冲器数据的比特流组合以将光标特性覆盖在视频显示数据上。 因此，光标数据缓冲器可以相对较小，但是通过控制视频显示的计算机的最小化操作覆盖相对大的光标。