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1.发明授权Logical drawing and transparency circuits for bit mapped video display controllers 失效位映像视频显示控制器的逻辑图和透明电路
公开(公告)号：US4893116A
公开(公告)日：1990-01-09
申请号：US120902
申请日：1987-11-16
CPC分类号： G09G5/022
摘要： An interface controller, situated between a graphics controller and a memory array in a color video display system operable in a read-modify-write mode, configured to detect a select transparency color in whole or in part and to respond by selectively changing the color binary data for the corresponding pixel in a frame buffer. In another aspect, the invention includes drawing modes impelmented by logically combining pixel color binary data in accordance with a defined truth table so as to allow the pixel color data representing a new image to interact in a defined manner based upon color with the data in a previously defined image. As implemented, the binary data in the frame buffer is acted upon in a read-modify-write sequence whereby the various logic operations analyze the source (foreground) pixel data, the destination (background) pixel data, in the context of control signals, to define the pixel color data written into the frame buffer as the color representation for that pixel position.
摘要翻译： 位于彩色视频显示系统中的图形控制器和存储器阵列之间的接口控制器，其以读 - 修改 - 写模式操作，被配置为全部或部分地检测选择透明度颜色，并通过选择性地改变颜色二进制 帧缓冲器中相应像素的数据。 在另一方面，本发明包括通过根据定义的真值表逻辑地组合像素颜色二进制数据来驱动的绘制模式，以便允许表示新图像的像素颜色数据以定义的方式基于颜色与数据在 先前定义的图像。 如实现的，帧缓冲器中的二进制数据以读 - 修改 - 写序列的方式被执行，由此各种逻辑运算在控制信号的上下文中分析源（前景）像素数据，目的地（背景）像素数据， 将写入帧缓冲器的像素颜色数据定义为该像素位置的颜色表示。
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公开(公告)号：US5146211A
公开(公告)日：1992-09-08
申请号：US566014
申请日：1990-08-10
IPC分类号： G09G5/08
CPC分类号： G09G5/08
摘要： An architecture for generating a hardware cursor in the context of a bit mapped video display system operable from a frame buffer with non-displayed but addressable memory space. A segment of the non-displayed memory is loaded with cursor information controlling the generation of its outline and its color pattern. When accessed, this cursor control data is accessed from the non-displayed segment of the memory during each horizontal blank time preceding the raster scan of the video pattern data subject to cursor overlay. Location of the cursor within the video display is determined by a group of position registers which are loaded by the CPU with cursor position data during the vertical blank time. The position registers in conjunction with a group of counters coordinate the insertion of the cursor data into a byte stream of display data as it makes its way to the CRT screen. This display data is stored in the frame buffer and is transferred to the pixel output buffer. The display data in the pixel output buffer is subsequently interpreted into colors and intensities, and displayed on the CRT screen using known techniques. The vertical and horizontal locations of the cursor are synchronously incremented on a pixel by pixel basis during the scan of a frame buffer line. At the appropriate location, cursor data is multiplexed and/or logically combined with the bit stream of frame buffer data to overlay the cursor characteristics upon the video display data. The cursor data buffer can thereby be relatively small yet overlay a relatively large cursor with minimal manipulation by the computer controlling the video display.
摘要翻译： 一种用于在从具有非显示但可寻址的存储器空间的帧缓冲器中操作的位映射视频显示系统的上下文中生成硬件光标的架构。 未显示的存储器的段被加载有控制其轮廓及其颜色模式的生成的光标信息。 当访问时，在光标覆盖的视频图案数据的光栅扫描之前的每个水平空白时间期间，从存储器的未显示段访问该光标控制数据。 视频显示中的光标的位置由在垂直空白时间期间由CPU加载光标位置数据的一组位置寄存器确定。 位置寄存器结合一组计数器协调将光标数据插入到显示数据的字节流中，当它进入CRT屏幕时。 该显示数据被存储在帧缓冲器中并被传送到像素输出缓冲器。 像素输出缓冲器中的显示数据随后被解释为颜色和强度，并使用已知技术在CRT屏幕上显示。 在帧缓冲线的扫描期间，光标的垂直和水平位置在逐个像素的基础上同步递增。 在适当的位置，光标数据被多路复用和/或逻辑地与帧缓冲器数据的比特流组合以将光标特性覆盖在视频显示数据上。 因此，光标数据缓冲器可以相对较小，但是通过控制视频显示的计算机的最小化操作覆盖相对大的光标。
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公开(公告)号：US6000037A
公开(公告)日：1999-12-07
申请号：US996528
申请日：1997-12-23
申请人： Brian K. Herbert
发明人： Brian K. Herbert
摘要： A method for transferring data from a first clock domain to a second clock domain. A first clock signal is generated for the first clock domain from a base clock signal. A second clock signal is generated for the second clock domain from the base clock signal. A phase relationship is detected between the first clock signal and the second clock signal. Data is transferred from the first clock domain to the second clock domain using the phase relationship between the first clock signal and the second clock signal.
摘要翻译： 一种用于将数据从第一时钟域传送到第二时钟域的方法。 从基本时钟信号为第一时钟域产生第一时钟信号。 从基本时钟信号产生第二时钟域的第二时钟信号。 在第一时钟信号和第二时钟信号之间检测相位关系。 使用第一时钟信号和第二时钟信号之间的相位关系，数据从第一时钟域传送到第二时钟域。
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公开(公告)号：US4902940A
公开(公告)日：1990-02-20
申请号：US279387
申请日：1988-12-02
申请人： Brian K. Herbert
发明人： Brian K. Herbert
CPC分类号： H01J37/24
摘要： A current control circuit is provided for a stigmator lens of an electron or ion beam machine. The stigmator lens consists of two magnetic quadrupole lenses, each of which has two pairs of coils. Current monitoring resistors R10,R11,R12 and R13 are connected in series with the individual coils L1,L2,L3 and L4 of the quadrupole and a resistor R3 is connected to monitor the sum of currents in the pairs of coils. Voltage signals from the resistors are used to close feedback loops which drive currents into the individual coils so that the sum of currents in a pair of coils is held constant at a value set by an adjustable astigmatism control and so that the ratio of the currents in a pair of coils is held constant at a value set by an adjustable beam centering control. Coil currents are stabilized in spite of coil resistance changes due to Joule heating by the currents. Computer control of astigmatism and centering is facilitated since only signal voltages are required as inputs to the circuit.
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公开(公告)号：US06255878B1
公开(公告)日：2001-07-03
申请号：US09307533
申请日：1999-05-07
IPC分类号： H03H1126
CPC分类号： H03K5/133
摘要： A precision delay circuit having two delay chains to provide equal delay periods is described. A rising edge of an input pulse signal is supplied to the first delay chain and the falling edge is supplied to the second delay chain. The resultant output signal maintains the pulse width of the input signal and pulse distortion is minimized. In another aspect, a delay circuit for generating a delayed assertion signal that does not maintain the width of the original input signal pulse and which is substantially immune to noise problems is described. An assertion edge of a resultant pulse is timed by the incoming pulse, but the de-assertion edge is timed by the delayed de-assertion edge of the incoming pulse.
摘要翻译： 描述了具有两个延迟链以提供相等的延迟周期的精度延迟电路。 输入脉冲信号的上升沿被提供给第一延迟链，下降沿被提供给第二延迟链。 所得到的输出信号保持输入信号的脉冲宽度，脉冲失真最小化。 在另一方面，描述了用于产生不维持原始输入信号脉冲的宽度并且基本上不受噪声问题的延迟的断言信号的延迟电路。 合成脉冲的断言边缘由输入脉冲定时，但去声明边沿由输入脉冲的延迟去激活边沿定时。
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公开(公告)号：US6049331A
公开(公告)日：2000-04-11
申请号：US065387
申请日：1993-05-20
申请人： Brian K. Herbert
发明人： Brian K. Herbert
CPC分类号： G09G5/393
摘要： The invention concerns loading data into VIDEO RAM in a computer. A processor delivers data to VIDEO RAM by using "STRING OPs," which are data-copying operations wherein a field of consecutive data words is copied from one location (such as character memory) to a range of consecutive addresses at another location (such as VIDEO RAM). The invention intercepts the words intended for the consecutive addresses, and distributes them into VIDEO RAM at evenly spaced, non-consecutive addresses. When a graphics controller generates pixels on a display, based on these evenly-spaced addresses, the pixels will automatically occupy a vertical column on the display.
摘要翻译： 本发明涉及将数据加载到计算机中的VIDEO RAM中。 处理器通过使用“STRING OP”将数据传送到VIDEO RAM，这是数据复制操作，其中将连续数据字的字段从一个位置（例如字符存储器）复制到另一位置的连续地址范围（例如 视频内存）。 本发明拦截了用于连续地址的字，并以均匀间隔的非连续地址将其分配到VIDEO RAM中。 当图形控制器在显示器上生成像素时，基于这些均匀间隔的地址，像素将自动占据显示屏上的垂直列。
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7.发明授权Image processing apparatus including horizontal and vertical scaling for a computer display 失效图像处理装置，包括用于计算机显示器的水平和垂直缩放
公开(公告)号：US6014125A
公开(公告)日：2000-01-11
申请号：US352401
申请日：1994-12-08
申请人： Brian K. Herbert
发明人： Brian K. Herbert
CPC分类号： G06T3/4015 , G09G5/391 , G09G2340/0414 , G09G2340/0421
摘要： A scaling apparatus is disclosed for horizontally and vertically scaling scan line information stored in a video memory prior to providing the scan line information to a computer display. Horizontal scaling apparatus is provided in which a first clock signal is provided for graphics portions of scan lines and a second clock signal is provided for video portions of scan lines. The second clock signal is enabled in a manner such that the second clock signal exhibits a predetermined phase relationship with respect to the first clock signal from scan line to scan line. The frequency of the second clock signal is selected to determine the scaling of the video portion of the scan line. Vertical scaling apparatus is provided in which scan line information corresponding to first and second scan lines is retrieved from a video memory. A digital differential analyzer, external to the central processing unit, then determines respective weights for the first and second scan lines dependent on the amount of vertical scaling desired. The weights for the first and second scan lines are then provided to a weighted adder which adds the first and second scan lines according to these weights.
摘要翻译： 公开了一种缩放装置，用于在将扫描线信息提供给计算机显示器之前水平和垂直缩放存储在视频存储器中的扫描线信息。 提供了水平缩放装置，其中为扫描线的图形部分提供第一时钟信号，并且为扫描线的视频部分提供第二时钟信号。 第二时钟信号以使得第二时钟信号相对于从扫描线到扫描线的第一时钟信号呈现预定的相位关系的方式被使能。 选择第二时钟信号的频率以确定扫描线的视频部分的缩放。 提供了垂直缩放装置，其中从视频存储器检索对应于第一和第二扫描线的扫描线信息。 取决于所需的垂直缩放量，在中央处理单元外部的数字差分分析仪确定第一和第二扫描线的相应权重。 然后将第一和第二扫描线的权重提供给加权加法器，该加权加法器根据这些权重添加第一和第二扫描线。
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公开(公告)号：US5777596A
公开(公告)日：1998-07-07
申请号：US556689
申请日：1995-11-13
申请人： Brian K. Herbert
发明人： Brian K. Herbert
CPC分类号： G06F3/0412 , G02F1/13338
摘要： The present invention relates to a touch sensitive LCD flat panel display. The display allows a user to provide input into a computer device by simply touching an LCD display screen with a passive device, such as a finger, stylus, or a ball point pen. The invention includes circuitry which continuously compares the charge times of the liquid crystal elements of the display to a reference value and uses the results of the comparison to determine which elements in the display are currently being touched.
摘要翻译： 本发明涉及一种触敏LCD平板显示器。 显示器允许用户通过简单地用诸如手指，触笔或圆珠笔的无源设备触摸LCD显示屏来向计算机设备提供输入。 本发明包括将显示器的液晶元件的充电时间连续地与参考值进行比较的电路，并且使用比较结果来确定显示器中的哪些元件当前正被触摸。
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公开(公告)号：US5644336A
公开(公告)日：1997-07-01
申请号：US355413
申请日：1994-12-12
申请人： Brian K. Herbert
发明人： Brian K. Herbert
摘要： The invention concerns the simultaneous display of video data and text data on a computer display. The invention stores both types of data in display memory. Transition codes mark the separation between the two types. The invention converts each type of data into signals which a CRT display can understand. The invention changes the type of conversion, as appropriate, when transition codes are reached.
摘要翻译： 本发明涉及在计算机显示器上同时显示视频数据和文本数据。 本发明将两种类型的数据存储在显示存储器中。 转换代码标记了两种类型之间的分离。 本发明将每种类型的数据转换为CRT显示器可以理解的信号。 当达到转换代码时，本发明适当地改变转换类型。
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10.发明授权Method and apparatus for utilizing a data processing system for multi-level data communications providing self-clocking 失效用于提供自我定时的多级数据通信的数据处理系统的方法和装置公开(公告)号：US06317469B1
公开(公告)日：2001-11-13
申请号：US08673390
申请日：1996-06-28
申请人： Brian K. Herbert
发明人： Brian K. Herbert
IPC分类号： H04L2549
CPC分类号： H04L25/4904 , H04L25/063
摘要： A method and apparatus utilizing a data processing system are disclosed for multi-level data communication providing self-clocking. A first digital signal is input which includes a series of digital bits. One of a plurality of output levels is associated with each group of data bits for each of the plurality of the digital bits included within the first digital signal. A particular output level is associated with a clock output level. An output signal is generate which includes a transmission of the output level for each of the groups of digital bits and includes multiple transmissions of the clock output level, where a clock output level is transmitted after each transmission of an output level for each of the groups of digital bits.
摘要翻译： 公开了一种利用数据处理系统的方法和装置，用于提供自我定时的多级数据通信。 输入第一数字信号，其包括一系列数字位。 多个输出电平中的一个与包含在第一数字信号内的多个数字位中的每个数字位相关联。 特定的输出电平与时钟输出电平相关联。 产生一个输出信号，其中包括数字比特组中的每一组的输出电平的传输，并且包括时钟输出电平的多个传输，其中在每个发送每个组的输出电平的每个发送之后发送时钟输出电平 的数字位。
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