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1.发明授权公开(公告)号：US08423329B2
公开(公告)日：2013-04-16
申请号：US12691415
申请日：2010-01-21
申请人： Seong-Ook Jung , Jisu Kim , Jee-Hwan Song , Seung H. Kang
发明人： Seong-Ook Jung , Jisu Kim , Jee-Hwan Song , Seung H. Kang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/10 , G11C7/02 , G11C7/06 , G11C11/1673
摘要： Systems and methods of resistance-based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance-based memory circuit includes determining a range of sizes for a clamp transistor and selecting a set of clamp transistors having sizes within the determined range of sizes. For each clamp transistor in the set of clamp transistors, a simulation may be executed to generate a first contour graph representing current values over a range of statistical values. The first contour graph may be used to identify a read disturbance area and a design range of the gate voltage of the clamp transistor and a load of the clamp transistor. The method may execute a simulation to generate a second contour graph representing sense margin over a range of statistical values of the gate voltage of the clamp transistor and the load of the clamp transistor. A sense margin may be selected based on the second contour graph that also satisfies the design range of the first contour graph. A sense margin may be determined for a selected clamp transistor in the set of transistors and the corresponding gate voltage and the load of the selected clamp transistor is determined based on the determined sense margin.
摘要翻译： 公开了基于电阻的存储器电路参数调整的系统和方法。 在特定实施例中，确定基于电阻的存储器电路的一组参数的方法包括确定钳位晶体管的尺寸范围，并选择尺寸在所确定的尺寸范围内的一组钳位晶体管。 对于钳位晶体管组中的每个钳位晶体管，可以执行仿真以生成表示一定范围的统计值的当前值的第一轮廓图。 第一轮廓图可以用于识别钳位晶体管的栅极电压和钳位晶体管的负载的读取扰动区域和设计范围。 该方法可以执行仿真以产生表示钳位晶体管的栅极电压和钳位晶体管的负载的统计值范围内的检测余量的第二轮廓图。 可以基于也满足第一轮廓图的设计范围的第二轮廓图来选择感测余量。 可以针对晶体管组中的选定的钳位晶体管确定感测余量，并且基于所确定的感测余量来确定相应的栅极电压，并且选择的钳位晶体管的负载被确定。
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公开(公告)号：US07813166B2
公开(公告)日：2010-10-12
申请号：US12164436
申请日：2008-06-30
申请人： Seong-Ook Jung , Jisu Kim , Jee-Hwan Song , Seung H. Kang , Sei Seung Yoon
发明人： Seong-Ook Jung , Jisu Kim , Jee-Hwan Song , Seung H. Kang , Sei Seung Yoon
IPC分类号： G11C7/00
CPC分类号： G11C7/14 , G11C11/1673 , G11C13/0002 , G11C13/004 , G11C2013/0054
摘要： Systems and methods of controlled value reference signals of resistance based memory circuits are disclosed. In a particular embodiment, a circuit device is disclosed that includes a first input configured to receive a reference control signal. The circuit device also includes an output responsive to the first input to selectively provide a controlled value reference voltage to a sense amplifier coupled to a resistance based memory cell.
摘要翻译： 公开了基于电阻的存储器电路的受控值参考信号的系统和方法。 在特定实施例中，公开了一种电路装置，其包括被配置为接收参考控制信号的第一输入。 电路装置还包括响应于第一输入的输出，以选择性地向耦合到基于电阻的存储器单元的读出放大器提供受控值参考电压。
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公开(公告)号：US07889585B2
公开(公告)日：2011-02-15
申请号：US12338297
申请日：2008-12-18
申请人： Seong-Ook Jung , Jisu Kim , Jee-Hwan Song , Seung H. Kang , Sei Seung Yoon , Mehdi Hamidi Sani
发明人： Seong-Ook Jung , Jisu Kim , Jee-Hwan Song , Seung H. Kang , Sei Seung Yoon , Mehdi Hamidi Sani
IPC分类号： G11C7/00
CPC分类号： G11C7/14 , G11C7/12 , G11C11/1673
摘要： A resistance based memory circuit is disclosed. The circuit includes a first transistor load of a data cell and a bit line adapted to detect a first logic state. The bit line is coupled to the first transistor load and coupled to a data cell having a magnetic tunnel junction (MTJ) structure. The bit line is adapted to detect data having a logic one value when the bit line has a first voltage value, and to detect data having a logic zero value when the bit line has a second voltage value. The circuit further includes a second transistor load of a reference cell. The second transistor load is coupled to the first transistor load, and the second transistor load has an associated reference voltage value. A characteristic of the first transistor load, such as transistor width, is adjustable to modify the first voltage value and the second voltage value without substantially changing the reference voltage value.
摘要翻译： 公开了一种基于电阻的存储器电路。 电路包括数据单元的第一晶体管负载和适于检测第一逻辑状态的位线。 位线耦合到第一晶体管负载并耦合到具有磁隧道结（MTJ）结构的数据单元。 当位线具有第一电压值时，位线适于检测具有逻辑1值的数据，并且当位线具有第二电压值时检测具有逻辑零值的数据。 电路还包括参考单元的第二晶体管负载。 第二晶体管负载耦合到第一晶体管负载，并且第二晶体管负载具有相关联的参考电压值。 第一晶体管负载（例如晶体管宽度）的特性是可调节的，以修改第一电压值和第二电压值，而基本上不改变参考电压值。
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公开(公告)号：US20090323405A1
公开(公告)日：2009-12-31
申请号：US12164436
申请日：2008-06-30
申请人： Seong-Ook Jung , Ji-Su Kim , Jee-Hwan Song , Seung H. Kang , Sei Seung Yoon
发明人： Seong-Ook Jung , Ji-Su Kim , Jee-Hwan Song , Seung H. Kang , Sei Seung Yoon
CPC分类号： G11C7/14 , G11C11/1673 , G11C13/0002 , G11C13/004 , G11C2013/0054
摘要： Systems and methods of controlled value reference signals of resistance based memory circuits are disclosed. In a particular embodiment, a circuit device is disclosed that includes a first input configured to receive a reference control signal. The circuit device also includes an output responsive to the first input to selectively provide a controlled value reference voltage to a sense amplifier coupled to a resistance based memory cell.
摘要翻译： 公开了基于电阻的存储器电路的受控值参考信号的系统和方法。 在特定实施例中，公开了一种电路装置，其包括被配置为接收参考控制信号的第一输入。 电路装置还包括响应于第一输入的输出，以选择性地向耦合到基于电阻的存储器单元的读出放大器提供受控值参考电压。
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5.发明申请公开(公告)号：US20090265678A1
公开(公告)日：2009-10-22
申请号：US12107252
申请日：2008-04-22
申请人： Seong-Ook Jung , Jisu Kim , Jee-Hwan Song , Seung H. Kang , Sei Seung Yoon
发明人： Seong-Ook Jung , Jisu Kim , Jee-Hwan Song , Seung H. Kang , Sei Seung Yoon
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F17/5036 , G06F17/5059 , G11C11/1673
摘要： Systems and methods of resistance based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance based memory circuit includes selecting a first parameter based on a first predetermined design constraint of the resistance based memory circuit and selecting a second parameter based on a second predetermined design constraint of the resistance based memory circuit. The method further includes performing an iterative methodology to adjust at least one circuit parameter of a sense amplifier portion of the resistance based memory circuit by selectively assigning and adjusting a physical property of the at least one circuit parameter to achieve a desired sense amplifier margin value without changing the first parameter or the second parameter.
摘要翻译： 公开了基于电阻的存储器电路参数调整的系统和方法。 在特定实施例中，确定基于电阻的存储器电路的一组参数的方法包括基于基于电阻的存储器电路的第一预定设计约束来选择第一参数，并且基于第二预定设计约束来选择第二参数 电阻式存储电路。 该方法还包括执行迭代方法以通过选择性地分配和调整至少一个电路参数的物理特性来调整基于电阻的存储器电路的读出放大器部分的至少一个电路参数，以实现期望的读出放大器余量值，而没有 改变第一个参数或第二个参数。
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6.发明授权公开(公告)号：US08161430B2
公开(公告)日：2012-04-17
申请号：US12107252
申请日：2008-04-22
申请人： Seong-Ook Jung , Jisu Kim , Jee-Hwan Song , Seung H. Kang , Sei Seung Yoon
发明人： Seong-Ook Jung , Jisu Kim , Jee-Hwan Song , Seung H. Kang , Sei Seung Yoon
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F17/5036 , G06F17/5059 , G11C11/1673
摘要： Systems and methods of resistance based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance based memory circuit includes selecting a first parameter based on a first predetermined design constraint of the resistance based memory circuit and selecting a second parameter based on a second predetermined design constraint of the resistance based memory circuit. The method further includes performing an iterative methodology to adjust at least one circuit parameter of a sense amplifier portion of the resistance based memory circuit by selectively assigning and adjusting a physical property of the at least one circuit parameter to achieve a desired sense amplifier margin value without changing the first parameter or the second parameter.
摘要翻译： 公开了基于电阻的存储器电路参数调整的系统和方法。 在特定实施例中，确定基于电阻的存储器电路的一组参数的方法包括基于基于电阻的存储器电路的第一预定设计约束来选择第一参数，并且基于第二预定设计约束来选择第二参数 电阻式存储电路。 该方法还包括执行迭代方法以通过选择性地分配和调整至少一个电路参数的物理特性来调整基于电阻的存储器电路的读出放大器部分的至少一个电路参数，以实现期望的读出放大器余量值，而没有 改变第一个参数或第二个参数。
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7.发明申请公开(公告)号：US20110178768A1
公开(公告)日：2011-07-21
申请号：US12691415
申请日：2010-01-21
申请人： Seong-Ook Jung , Jisu Kim , Jee-Hwan Song , Seung H. Kang
发明人： Seong-Ook Jung , Jisu Kim , Jee-Hwan Song , Seung H. Kang
CPC分类号： G06F17/5036 , G06F2217/10 , G11C7/02 , G11C7/06 , G11C11/1673
摘要： Systems and methods of resistance-based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance-based memory circuit includes determining a range of sizes for a clamp transistor and selecting a set of clamp transistors having sizes within the determined range of sizes. For each clamp transistor in the set of clamp transistors, a simulation may be executed to generate a first contour graph representing current values over a range of statistical values. The first contour graph may be used to identify a read disturbance area and a design range of the gate voltage of the clamp transistor and a load of the clamp transistor. The method may execute a simulation to generate a second contour graph representing sense margin over a range of statistical values of the gate voltage of the clamp transistor and the load of the clamp transistor. A sense margin may be selected based on the second contour graph that also satisfies the design range of the first contour graph. A sense margin may be determined for a selected clamp transistor in the set of transistors and the corresponding gate voltage and the load of the selected clamp transistor is determined based on the determined sense margin.
摘要翻译： 公开了基于电阻的存储器电路参数调整的系统和方法。 在特定实施例中，确定基于电阻的存储器电路的一组参数的方法包括确定钳位晶体管的尺寸范围，并选择尺寸在所确定的尺寸范围内的一组钳位晶体管。 对于钳位晶体管组中的每个钳位晶体管，可以执行仿真以生成表示一定范围的统计值的当前值的第一轮廓图。 第一轮廓图可以用于识别钳位晶体管的栅极电压和钳位晶体管的负载的读取扰动区域和设计范围。 该方法可以执行仿真以产生表示钳位晶体管的栅极电压和钳位晶体管的负载的统计值范围内的检测余量的第二轮廓图。 可以基于也满足第一轮廓图的设计范围的第二轮廓图来选择感测余量。 可以针对晶体管组中的选定的钳位晶体管确定感测余量，并且基于所确定的感测余量来确定对应的栅极电压并且选择钳位晶体管的负载。
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公开(公告)号：US20100157654A1
公开(公告)日：2010-06-24
申请号：US12338297
申请日：2008-12-18
申请人： Seong-Ook Jung , Jisu Kim , Jee-Hwan Song , Seung H. Kang , Sei Seung Yoon , Mehdi Hamidi Sani
发明人： Seong-Ook Jung , Jisu Kim , Jee-Hwan Song , Seung H. Kang , Sei Seung Yoon , Mehdi Hamidi Sani
CPC分类号： G11C7/14 , G11C7/12 , G11C11/1673
摘要： A resistance based memory circuit is disclosed. The circuit includes a first transistor load of a data cell and a bit line adapted to detect a first logic state. The bit line is coupled to the first transistor load and coupled to a data cell having a magnetic tunnel junction (MTJ) structure. The bit line is adapted to detect data having a logic one value when the bit line has a first voltage value, and to detect data having a logic zero value when the bit line has a second voltage value. The circuit further includes a second transistor load of a reference cell. The second transistor load is coupled to the first transistor load, and the second transistor load has an associated reference voltage value. A characteristic of the first transistor load, such as transistor width, is adjustable to modify the first voltage value and the second voltage value without substantially changing the reference voltage value.
摘要翻译： 公开了一种基于电阻的存储器电路。 电路包括数据单元的第一晶体管负载和适于检测第一逻辑状态的位线。 位线耦合到第一晶体管负载并耦合到具有磁隧道结（MTJ）结构的数据单元。 当位线具有第一电压值时，位线适于检测具有逻辑1值的数据，并且当位线具有第二电压值时检测具有逻辑零值的数据。 电路还包括参考单元的第二晶体管负载。 第二晶体管负载耦合到第一晶体管负载，并且第二晶体管负载具有相关联的参考电压值。 第一晶体管负载（例如晶体管宽度）的特性是可调节的，以修改第一电压值和第二电压值，而基本上不改变参考电压值。
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