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    CURRENT REFERENCES FOR MEMORY CELLS
    1.
    发明公开
    CURRENT REFERENCES FOR MEMORY CELLS 审中-公开

    公开(公告)号：US20240203490A1

    公开(公告)日：2024-06-20

    申请号：US18590692

    申请日：2024-02-28

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi ,  Pierguido Garofalo ,  Umberto Di Vincenzo ,  Claudia Palattella

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C2013/0054

    Abstract: A variety of applications can include one or more memory devices having one or more memory arrays of memory cells, where each memory cell is a resistive memory cell arranged such that a clamp current for the memory cell can be provided by an access line biasing circuit to the memory cell opposite a coupling of a sense circuit to a digit line to the memory array. The access line biasing circuit and the sense circuit can be operated in a digit line precharge phase and an access line biasing phase of a memory cell of the memory array using a set of switches to control activities for the memory cell in the memory array, the sense circuit, and the access line biasing circuit. A reference current can be provided from the access line biasing circuit to the sense circuit. Additional devices, systems, and methods are discussed.

    Resistive memory device for writing data and operating method thereof
    2.
    发明授权
    Resistive memory device for writing data and operating method thereof 有权

    公开(公告)号：US11935592B2

    公开(公告)日：2024-03-19

    申请号：US17328248

    申请日：2021-05-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chankyung Kim

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C2013/0054

    Abstract: A resistive memory device includes a resistive cell connected between a first bit line and a first source line, a reference cell including a reference resistor and connected between a second bit line and a second source line, and a write driver connected to the first bit line or the first source line, connected to the second bit line or the second source line. The write driver includes a comparator configured to compare previous data written in the resistive cell with the target data by comparing a voltage of the first source line with a voltage of the second source line or comparing a voltage of the first bit line with a voltage of the second bit line, and determine whether the target data is written in the resistive cell after comparing the previous data with the target data.

    Neuromorphic computing device and method of designing the same
    3.
    发明授权
    Neuromorphic computing device and method of designing the same 有权

    公开(公告)号：US11881260B2

    公开(公告)日：2024-01-23

    申请号：US17538235

    申请日：2021-11-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngnam Hwang

    IPC: G06N3/063 ,  G11C13/00 ,  G11C7/16 ,  G11C11/54

    CPC classification number: G11C13/004 ,  G11C7/16 ,  G11C11/54 ,  G11C13/0026 ,  G11C13/0069 ,  G11C2013/0054

    Abstract: A neuromorphic computing device includes first and second memory cell arrays, and an analog-to-digital converting circuit. The first memory cell array includes a plurality of resistive memory cells, generates a plurality of read currents based on a plurality of input signals and a plurality of data, and outputs the plurality of read currents through a plurality of bitlines or source lines. The second memory cell array includes a plurality of reference resistive memory cells and an offset resistor, and outputs a reference current through a reference bitline or a reference source line. The analog-to-digital converting circuit converts the plurality of read currents into a plurality of digital signals based on the reference current. The offset resistor is connected between the reference bitline and the reference source line.

    CURRENT REFERENCES FOR MEMORY CELLS
    5.
    发明公开
    CURRENT REFERENCES FOR MEMORY CELLS 审中-公开

    公开(公告)号：US20230335191A1

    公开(公告)日：2023-10-19

    申请号：US17720957

    申请日：2022-04-14

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi ,  Pierguido Garofalo ,  Umberto Di Vincenzo ,  Claudia Palattella

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C2013/0054

    Abstract: A variety of applications can include one or more memory devices having one or more memory arrays of memory cells, where each memory cell is a resistive memory cell arranged such that a clamp current for the memory cell can be provided by an access line biasing circuit to the memory cell opposite a coupling of a sense circuit to a digit line to the memory array. The access line biasing circuit and the sense circuit can be operated in a digit line precharge phase and an access line biasing phase of a memory cell of the memory array using a set of switches to control activities for the memory cell in the memory array, the sense circuit, and the access line biasing circuit. A reference current can be provided from the access line biasing circuit to the sense circuit. Additional devices, systems, and methods are discussed.

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