摘要:
A method of multiplying 32-bit values includes decomposing each multiplicand into its 16-bit components. This approach leads to a processor core design which permits re-use of much of the logic in the multiplication unit. The multiplication unit includes a selector which can feed various-sized data formats to the same multiplier circuits. Multiple data transformation paths are provided and feed into a single compression circuit and a single configurable full adder circuit.
摘要:
A CMOS output buffer has as pull-downs a smaller driver transistor and a larger driver transistor. Both transistors drive the output low in parallel initially during a voltage transition, but the larger transistor is disabled for the remainder of the output voltage swing when reflections and ringing occur. A pulse is generated by a transition detector when an input to the output buffer transitions low. The pulse generated disables the larger driver for a short period of time but later re-enables the driver. Thus the large driver remains on after the switching is complete, providing large IOH and IOL static currents. The pulse is long enough to keep the large driver disabled while reflections are received and ringing occurs after the voltage transition. A Resistor in series with the smaller driver transistor absorbs these reflections. The output impedance is pulsed to the higher impedance of the first stage when ringing occurs at the end of the voltage transition, but after the pulse ends, the lower impedance of the large driver is seen. Pulses are generated when any neighboring output changes. The pulse generated is sent to all neighboring output buffers to disable their large drivers when noise in injected into the power or ground supplies.