公开(公告)号：US6027997A

公开(公告)日：2000-02-22

申请号：US205423

申请日：1994-03-04

申请人： Chris C. Yu ,  Jeffrey F. Hanson ,  Jeffrey L. Klein

发明人： Chris C. Yu ,  Jeffrey F. Hanson ,  Jeffrey L. Klein

IPC分类号： H01L21/304 ,  B24B37/00 ,  C09K13/04 ,  C23F1/00 ,  H01L21/321 ,  H01L21/768 ,  B44C1/22 ,  H01L21/306

CPC分类号： H01L21/3212

摘要： Conductive plugs (28) are formed in a semiconductor device (10) using a chemical mechanical polishing (CMP) process. A blanket conductive layer (26), for example of tungsten, is deposited in a plug opening (24). The conductive layer is polished back by CMP using a slurry comprised of either copper sulfate (CuSO.sub.4) or copper perchlorate [Cu(ClO.sub.4).sub.2 ] and an abrasive, such as alumina or silica, and water. In another embodiment, a CMP process using such slurries may be used to form conductive interconnects (50) in a semiconductor device (40).

摘要翻译： 使用化学机械抛光（CMP）工艺在半导体器件（10）中形成导电插塞（28）。 诸如钨的覆盖层导电层（26）沉积在插头开口（24）中。 使用由硫酸铜（CuSO 4）或高氯酸铜[Cu（ClO 4）2]和研磨剂如氧化铝或二氧化硅和水组成的浆料，通过CMP对导电层进行抛光。 在另一个实施例中，使用这种浆料的CMP工艺可用于在半导体器件（40）中形成导电互连（50）。

公开(公告)号：US07114143B2

公开(公告)日：2006-09-26

申请号：US10696203

申请日：2003-10-29

申请人： Jeffrey F. Hanson ,  Ryan C. Fredrickson

发明人： Jeffrey F. Hanson ,  Ryan C. Fredrickson

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G01N21/95684 ,  G05B2219/32187 ,  G05B2219/45031 ,  Y02P90/22

摘要： A method for producing yield enhancement data from integrated circuits on a substrate. A database of defects on the substrate is compared to a database of design information for the integrated circuits. The defects on the substrate are associated with classes of design information to produce the yield enhancement data.

摘要翻译： 一种用于从基板上的集成电路产生屈服增强数据的方法。 将基板上的缺陷数据库与用于集成电路的设计信息的数据库进行比较。 衬底上的缺陷与设计信息的类别相关联，以产生产量增强数据。

公开(公告)号：US07081379B2

公开(公告)日：2006-07-25

申请号：US11058498

申请日：2005-02-15

申请人： Jeffrey F. Hanson ,  Derryl D. J. Allman

发明人： Jeffrey F. Hanson ,  Derryl D. J. Allman

IPC分类号： H01L21/8238

CPC分类号： H01L23/535 ,  H01L21/76895 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit having a gate region, a source drain region, and an electrically nonconductive spacer separating the gate region and the source drain region. A local interconnect electrically connects the gate region to the source drain region across the electrically nonconductive spacer. The local interconnect is formed of a semiconducting material reacted with a metal. The local interconnect may be formed by implanting a precursor species into the electrically nonconductive spacer. A metal layer is deposited over at least the electrically nonconductive spacer, and the integrated circuit is heated to form an electrically conductive local interconnect from the metal layer and the precursor species implanted in the electrically nonconductive spacer.

公开(公告)号：US06872612B2

公开(公告)日：2005-03-29

申请号：US10383149

申请日：2003-03-06

申请人： Jeffrey F. Hanson ,  Derryl D. J. Allman

发明人： Jeffrey F. Hanson ,  Derryl D. J. Allman

IPC分类号： H01L21/768 ,  H01L23/535 ,  H01L21/8238

CPC分类号： H01L23/535 ,  H01L21/76895 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit having a gate region, a source drain region, and an electrically nonconductive spacer separating the gate region and the source drain region. A local interconnect electrically connects the gate region to the source drain region across the electrically nonconductive spacer. The local interconnect is formed of a semiconducting material reacted with a metal. The local interconnect may be formed by implanting a precursor species into the electrically nonconductive spacer. A metal layer is deposited over at least the electrically nonconductive spacer, and the integrated circuit is heated to form an electrically conductive local interconnect from the metal layer and the precursor species implanted in the electrically nonconductive spacer.