公开(公告)号：US20090150720A1

公开(公告)日：2009-06-11

申请号：US11951924

申请日：2007-12-06

申请人： Jehoda Rafaeli ,  Florian Bogenberger ,  James B. Eifert

发明人： Jehoda Rafaeli ,  Florian Bogenberger ,  James B. Eifert

IPC分类号： G06F11/10

CPC分类号： G06F11/1064 ,  G06F12/0864 ,  G06F12/126 ,  G06F2212/601

摘要： A data processing system includes a processor having a multi-way cache which has a first and a second way. The second way is configurable to either be redundant to the first way or to operate as an associative way independent of the first way. The system may further include a memory, where the processor, in response to a read address missing in the cache, provides the read address to the memory. The second way may be dynamically configured to be redundant to the first way during operation of the processor in response to an error detection signal. In one aspect, when the second way is configured to be redundant, in response to the read address hitting in the cache, data addressed by an index portion of the read address is provided from both the first and second way and compared to each other to determine if a comparison error exists.

摘要翻译： 数据处理系统包括具有第一和第二方式的多路缓存的处理器。 第二种方式是配置为第一种方式是冗余的，或作为独立于第一种方式的关联方式运行。 系统还可以包括存储器，其中响应于高速缓存中缺少的读取地址的处理器将读取地址提供给存储器。 响应于错误检测信号，在处理器的操作期间，第二种方式可被动态配置为在第一种方式中是冗余的。 在一个方面，当第二种方式被配置为冗余时，响应于高速缓存中的读取地址，由读取地址的索引部分寻址的数据从第一和第二方式提供并相互比较 确定是否存在比较错误。