公开(公告)号：US07532046B2

公开(公告)日：2009-05-12

申请号：US11632031

申请日：2005-06-30

申请人： Jelle Nico Wolthek ,  Cornelis Klaas Waardenburg ,  Cecilius Gerardus Kwakernaat ,  Stefan Gerhard Erich Butselaar

发明人： Jelle Nico Wolthek ,  Cornelis Klaas Waardenburg ,  Cecilius Gerardus Kwakernaat ,  Stefan Gerhard Erich Butselaar

IPC分类号： H03B1/00

CPC分类号： H04L25/0296 ,  H03F3/45991 ,  H03F2203/45538 ,  H03F2203/45588 ,  H03F2203/45616 ,  H04L25/0274

摘要： The invention relates to a receiver for a differential bus with a switch control logic (151), with two branches with resistive elements (7, 61 . . . 70, 8 and 5, 11 . . . 20, 6) and with switches (3, 80) for switching the resistive elements, in which the switch control logic sets the switches—in a first routine for determining the absolute level of signals on the bus by applying a common mode voltage to the bus, by comparing the voltage on a first resistive branch with a reference voltage, by selecting the correct switch settings, and by writing these settings to an internal storage device,—and in a second routine for minimizing the mismatch between the two resistive branches by applying a common mode voltage to the bus, by comparing the voltage of the second resistive branch with that of the already trimmed first resistive branch, by selecting the correct switch settings for the second branch, and by writing these settings to an internal storage device. The receiver therefore provides good balancing and common mode rejection.

摘要翻译： 本发明涉及一种具有开关控制逻辑（151）的差分总线的接收器，其具有两个具有电阻元件（7,61。，70,8和5,11，...，20,6）的分支以及开关（ 3，80），用于切换电阻元件，其中开关控制逻辑将开关置于用于通过向总线施加共模电压来确定总线上的信号的绝对电平的第一例程中，通过比较 具有参考电压的第一电阻分支，通过选择正确的开关设置，以及将这些设置写入内部存储装置，以及在第二程序中，通过向总线施加共模电压来最小化两个电阻分支之间的失配 通过比较第二电阻分支的电压与已修整的第一电阻分支的电压，通过选择第二分支的正确开关设置，并将这些设置写入内部存储装置。 因此，接收机提供良好的平衡和共模抑制。

公开(公告)号：US08189691B2

公开(公告)日：2012-05-29

申请号：US11632028

申请日：2005-06-30

申请人： Jelle Nico Wolthek ,  Cornelis Klass Waardenburg ,  Cecilius Gerardus Kwakernaat ,  Stefan Gerhard Erich Butselaar

发明人： Jelle Nico Wolthek ,  Cornelis Klass Waardenburg ,  Cecilius Gerardus Kwakernaat ,  Stefan Gerhard Erich Butselaar

IPC分类号： H04L25/00

CPC分类号： G06F13/4072 ,  H03F2203/7203 ,  H04L25/0272 ,  H04L25/0292

摘要： The invention relates to a receiver for a differential data bus with two resistive branches (1, 2, 3; 4, 5, 6), with a differential amplifier with two transistors (9, 10), with a resistor (13), and with a control logic (16) that controls a switch (15) with which a current from a current source (14) is switchable to either side of the resistor (13), which resistor couples the two transistors (9, 10), and with two operational amplifiers (17, 18) which are coupled to the two transistors (9,10) of the differential amplifier with opposite poles, in which receiver the control logic detects from the output signals of the two operational amplifiers (17,18) whether a “0” or a “1” is expected on the bus and which receiver sets the switch (25) accordingly so that a comparison with the received bus signal is made.

摘要翻译： 本发明涉及一种具有两个电阻分支（1,2,3,4,5,6）的差分数据总线的接收机，具有带有电阻器（13）的具有两个晶体管（9,10）的差分放大器，以及 控制逻辑（16），其控制开关（15），来自电流源（14）的电流可通过该开关（15）切换到电阻器（13）的任一侧，哪个电阻器耦合两个晶体管（9,10），以及 其中两个运算放大器（17,18）耦合到具有相反极点的差分放大器的两个晶体管（9,10），其中控制逻辑从两个运算放大器（17,18）的输出信号中检测出， 在总线上是否期望“0”或“1”，并且相应地接收器设置开关（25），使得与所接收的总线信号进行比较。

公开(公告)号：US20110188606A1

公开(公告)日：2011-08-04

申请号：US11632028

申请日：2005-06-30

申请人： Jelle Nico Wolthek ,  Cornelis Klass Waardenburg ,  Cecilius Gerardus Kwakernaat ,  Stefan Gerhard Erich Butselaar

发明人： Jelle Nico Wolthek ,  Cornelis Klass Waardenburg ,  Cecilius Gerardus Kwakernaat ,  Stefan Gerhard Erich Butselaar

IPC分类号： H04L27/00

CPC分类号： G06F13/4072 ,  H03F2203/7203 ,  H04L25/0272 ,  H04L25/0292

摘要： The invention relates to a receiver for a differential data bus with two resistive branches (1, 2,3; 4, 5, 6), with a differential amplifier with two transistors (9, 10), with a resistor (13), and with a control logic (16) that controls a switch (15) with which a current from a current source (14) is switchable to either side of the resistor (13), which resistor couples the two transistors (9, 10), and with two operational amplifiers (17, 18) which are coupled to the two transistors (9,10) of the differential amplifier with opposite poles, in which receiver the control logic detects from the output signals of the two operational amplifiers (17,18) whether a “0” or a “1” is expected on the bus and which receiver sets the switch (25) accordingly so that a comparison with the received bus signal is made.

摘要翻译： 本发明涉及一种具有两个电阻分支（1,2,3,4,5,6）的差分数据总线的接收机，具有带有电阻器（13）的具有两个晶体管（9,10）的差分放大器，以及 控制逻辑（16），其控制开关（15），来自电流源（14）的电流可通过该开关（15）切换到电阻器（13）的任一侧，哪个电阻器耦合两个晶体管（9,10），以及 其中两个运算放大器（17,18）耦合到具有相反极点的差分放大器的两个晶体管（9,10），其中控制逻辑从两个运算放大器（17,18）的输出信号中检测出， 在总线上是否期望“0”或“1”，并且相应地接收器设置开关（25），使得与所接收的总线信号进行比较。

公开(公告)号：US20080265969A1

公开(公告)日：2008-10-30

申请号：US11632031

申请日：2005-06-30

申请人： Jelle Nico Wolthek ,  Cornelis Klaas Waardenburg ,  Cecilius Gerardus Kwakernaat ,  Stefan Gerhard Erich Butselaar

发明人： Jelle Nico Wolthek ,  Cornelis Klaas Waardenburg ,  Cecilius Gerardus Kwakernaat ,  Stefan Gerhard Erich Butselaar

IPC分类号： H03L5/00

CPC分类号： H04L25/0296 ,  H03F3/45991 ,  H03F2203/45538 ,  H03F2203/45588 ,  H03F2203/45616 ,  H04L25/0274

摘要： The invention relates to a receiver for a differential bus with a switch control logic (151), with two branches with resistive elements (7, 61 . . . 70, 8 and 5, 11 . . . 20, 6) and with switches (3, 80) for switching the resistive elements, in which the switch control logic sets the switches—in a first routine for determining the absolute level of signals on the bus by applying a common mode voltage to the bus, by comparing the voltage on a first resistive branch with a reference voltage, by selecting the correct switch settings, and by writing these settings to an internal storage device, —and in a second routine for minimizing the mismatch between the two resistive branches by applying a common mode voltage to the bus, by comparing the voltage of the second resistive branch with that of the already trimmed first resistive branch, by selecting the correct switch settings for the second branch, and by writing these settings to an internal storage device. The receiver therefore provides good balancing and common mode rejection.

摘要翻译： 本发明涉及一种具有开关控制逻辑（151）的差分总线的接收器，其具有两个具有电阻元件（7,61。，70,8和5,11，...，20,6）的分支以及开关（ 3，80），用于切换电阻元件，其中开关控制逻辑将开关设置在第一程序中，用于通过对总线施加共模电压来确定总线上的信号的绝对电平，通过比较 具有参考电压的第一电阻分支，通过选择正确的开关设置，以及将这些设置写入内部存储装置，以及在第二程序中，通过向总线施加共模电压来最小化两个电阻分支之间的失配 通过比较第二电阻分支的电压与已修整的第一电阻分支的电压，通过选择第二分支的正确开关设置，并将这些设置写入内部存储装置。 因此，接收机提供良好的平衡和共模抑制。