公开(公告)号：US5982683A

公开(公告)日：1999-11-09

申请号：US046404

申请日：1998-03-23

申请人： James A. Watson ,  Fabiano Fontana ,  Jenny Chui ,  Steve Choi ,  Benjamin Lau

发明人： James A. Watson ,  Fabiano Fontana ,  Jenny Chui ,  Steve Choi ,  Benjamin Lau

IPC分类号： G11C29/10 ,  G11C7/00

CPC分类号： G11C29/10

摘要： An enhanced method of testing semiconductor devices having nonvolatile elements by determining regions of the semiconductor having differing orders of probability that a defect will occur. The enhanced method of testing includes testing of regions from the highest probability to the lowest probability of having a defect. Nonvolatile memory elements in the region being tested are placed in a high impedance state, bypass circuits in the region being tested are activated to bypass the nonvolatile memory elements that control the state of elements in the region being tested and test vectors are applied to the elements that are controlled by the bypassed nonvolatile memory elements. This procedure is repeated for the next untested region having the highest probability of having a defect until all regions have been tested.

摘要翻译： 通过确定具有不同发生故障概率的半导体区域来测试具有非易失性元件的半导体器件的增强方法。 增强的测试方法包括从最高概率到具有缺陷的最低概率的区域的测试。 被测试区域中的非易失性存储元件被置于高阻抗状态，被测试区域中的旁路电路被激活以绕过控制待测区域中的元件状态的非易失性存储元件，测试矢量被应用于元件 由旁路非易失性存储元件控制。 对具有最大概率的缺陷的下一个未测试区域重复该过程，直到所有区域都已被测试为止。