公开(公告)号：US5982683A

公开(公告)日：1999-11-09

申请号：US046404

申请日：1998-03-23

申请人： James A. Watson ,  Fabiano Fontana ,  Jenny Chui ,  Steve Choi ,  Benjamin Lau

发明人： James A. Watson ,  Fabiano Fontana ,  Jenny Chui ,  Steve Choi ,  Benjamin Lau

IPC分类号： G11C29/10 ,  G11C7/00

CPC分类号： G11C29/10

摘要： An enhanced method of testing semiconductor devices having nonvolatile elements by determining regions of the semiconductor having differing orders of probability that a defect will occur. The enhanced method of testing includes testing of regions from the highest probability to the lowest probability of having a defect. Nonvolatile memory elements in the region being tested are placed in a high impedance state, bypass circuits in the region being tested are activated to bypass the nonvolatile memory elements that control the state of elements in the region being tested and test vectors are applied to the elements that are controlled by the bypassed nonvolatile memory elements. This procedure is repeated for the next untested region having the highest probability of having a defect until all regions have been tested.

摘要翻译： 通过确定具有不同发生故障概率的半导体区域来测试具有非易失性元件的半导体器件的增强方法。 增强的测试方法包括从最高概率到具有缺陷的最低概率的区域的测试。 被测试区域中的非易失性存储元件被置于高阻抗状态，被测试区域中的旁路电路被激活以绕过控制待测区域中的元件状态的非易失性存储元件，测试矢量被应用于元件 由旁路非易失性存储元件控制。 对具有最大概率的缺陷的下一个未测试区域重复该过程，直到所有区域都已被测试为止。

公开(公告)号：US20110114534A1

公开(公告)日：2011-05-19

申请号：US12922408

申请日：2009-03-13

申请人： James A. Watson ,  John Burns ,  Martin I. Forbes ,  Matthew A. Fuller ,  Mark V. Smith

发明人： James A. Watson ,  John Burns ,  Martin I. Forbes ,  Matthew A. Fuller ,  Mark V. Smith

IPC分类号： B65D85/86

CPC分类号： H01L21/67393

摘要： A wafer container utilizes a rigid polymer tubular tower with slots and a “getter” therein for absorbing and filtering moisture and vapors within the wafer container. The tower preferably utilizes a purge grommet at the base of the container and may have a check valve therein to control the flow direction of gas (including air) into and out of the container and with respect to the tower. The tower is sealingly connected with the grommet. The tower may have a getter media piece rolled in an elongate circular fashion forming or shaped as a tube and disposed within the tower and may have axially extending. The media can provide active and/or passive filtration as well as having capabilities to be recharged. Front opening wafer containers for 300 mm sized wafers generally have a pair of recesses on each of the left and right side in the inside rear of the container portions. These recesses are preferably utilized for elongate towers, such towers extending substantially from a bottom wafer position to a top wafer position. In alternative embodiment, a tubular shape of getter material is exposed within the front opening container without containment of the getter other than at the ends. The tubular getter form is preferably supported at discrete locations to maximize exposure to the internal container environment. A blocker member can selectively close the apertures. An elastomeric cap can facilitate securement of the tubular component in the container portion.

摘要翻译： 晶片容器利用具有槽的刚性聚合物管状塔和其中的“吸气剂”，用于吸收和过滤晶片容器内的水分和蒸气。 塔优选在容器的底部使用吹扫索环，并且可以在其中具有止回阀以控制进入和离开容器的气体（包括空气）的流动方向并相对于塔。 塔与护环密封连接。 塔可以具有以细长的圆形方式卷绕的吸气剂介质片，其形成或成形为管，并且设置在塔内并且可以具有轴向延伸。 介质可以提供主动和/或无源过滤以及具有再充电能力。 用于300mm尺寸晶片的前开口晶片容器通常在容器部分的内侧后部的左侧和右侧各具有一对凹部。 这些凹槽优选地用于细长塔，这种塔基本上从底部晶片位置延伸到顶部晶片位置。 在替代实施例中，吸气剂材料的管状形状暴露在前开口容器内，而不会吸收除了末端之外的吸气剂。 管状吸气剂形式优选地在离散位置处被支撑以最大程度地暴露于内部容器环境。 阻挡件可以选择性地封闭孔。 弹性帽可有助于管状部件固定在容器部分中。

公开(公告)号：USRE38651E1

公开(公告)日：2004-11-09

申请号：US09096917

申请日：1998-06-12

申请人： Chiakang Sung ,  Wanli Chang ,  Joseph Huang ,  Richard G. Cliff ,  L. Todd Cope ,  Cameron R. McClintock ,  William Leong ,  James A. Watson ,  Bahram Ahanin

发明人： Chiakang Sung ,  Wanli Chang ,  Joseph Huang ,  Richard G. Cliff ,  L. Todd Cope ,  Cameron R. McClintock ,  William Leong ,  James A. Watson ,  Bahram Ahanin

IPC分类号： G06F1200

CPC分类号： G11C8/12 ,  G01R31/318516

摘要： A programmable variable depth and width random-access memory circuit is provided. The memory circuit contains rows and columns of memory cells for storing data. A row decoder is used to address individual rows of the memory cells. Column address circuitry receives a column address signal and a width and depth selection signal. A column decoder within the column address circuitry addresses one or more columns of memory cells of the RAM array based on the selected width of the array. The output of the column decoder is routed to the appropriate column or columns of memory cells by a pattern of fixed connections and a group of programmable multiplexers. The number of data output lines to which data signals are provided is determined by the selected width of the RAM array. The output circuitry contains a group of programmable demultiplexers and a routing array having a pattern of fixed connections suitable for passing data signals from the RAM array to the selected number of data output lines.

公开(公告)号：US5668771A

公开(公告)日：1997-09-16

申请号：US655870

申请日：1996-05-24

申请人： Richard G. Cliff ,  L. Todd Cope ,  Cameron R. McClintock ,  William Leong ,  James A. Watson ,  Joseph Huang ,  Bahram Ahanin

发明人： Richard G. Cliff ,  L. Todd Cope ,  Cameron R. McClintock ,  William Leong ,  James A. Watson ,  Joseph Huang ,  Bahram Ahanin

IPC分类号： G01R31/3185 ,  G11C8/12 ,  H03K19/094 ,  H03K19/173 ,  H03K19/177 ,  G11C13/00 ,  G11B7/00

CPC分类号： H03K19/09429 ,  G11C8/12 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/1776 ,  H03K19/1778 ,  H03K19/17792 ,  G01R31/318516

摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

摘要翻译： 可编程逻辑阵列集成电路具有多个可编程逻辑模块，它们被组合在多个逻辑阵列块（“LAB”）中。 LAB以二维阵列布置在电路上。 提供一个导线网络，用于将任何逻辑模块与任何其他逻辑模块相互连接。 此外，相邻或附近的逻辑模块可以彼此连接，用于在逻辑模块之间提供进位链和/或用于将两个或多个模块连接在一起以提供更复杂的逻辑功能而不必利用一般互连的特殊目的 网络。 提供了所谓的快速或通用导体的另一网络，用于在整个电路中分布广泛使用的逻辑信号，例如时钟和清除信号。 多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。

公开(公告)号：US5268598A

公开(公告)日：1993-12-07

申请号：US043146

申请日：1993-03-31

申请人： Bruce B. Pedersen ,  David Chiang ,  Francis B. Heile ,  Cameron McClintock ,  Hock-Chuen So ,  James A. Watson

发明人： Bruce B. Pedersen ,  David Chiang ,  Francis B. Heile ,  Cameron McClintock ,  Hock-Chuen So ,  James A. Watson

IPC分类号： H03K19/173 ,  H03K19/177 ,  H03R19/177

CPC分类号： H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764 ,  H03K19/17784 ,  H03K19/17792

摘要： A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories.

摘要翻译： 提出了一种可编程逻辑器件，其包括全局互连阵列，其线路经由可编程多路复用器馈送到逻辑阵列块。 全局互连阵列线以特定模式馈送到多路复用器，其最大化用户将所选线路路由到所选择的多路复用器的输出的能力，同时保持更高的速度和更低的功耗，并且使用更少的芯片阵列 比使用基于可擦除可编程只读存储器的可编程互连阵列的现有技术的可编程逻辑器件。

公开(公告)号：US08783463B2

公开(公告)日：2014-07-22

申请号：US12922408

申请日：2009-03-13

申请人： James A. Watson ,  John Burns ,  Martin L. Forbes ,  Matthew A. Fuller ,  Mark V. Smith

发明人： James A. Watson ,  John Burns ,  Martin L. Forbes ,  Matthew A. Fuller ,  Mark V. Smith

IPC分类号： B65D85/00

CPC分类号： H01L21/67393

摘要： A wafer container utilizes a rigid polymer tubular tower with slots and a “getter” therein for absorbing and filtering moisture and vapors within the wafer container. The tower preferably utilizes a purge grommet at the base of the container and may have a check valve therein to control the flow direction of gas (including air) into and out of the container and with respect to the tower. The tower is sealingly connected with the grommet. The tower may have a getter media piece rolled in an elongate circular fashion forming or shaped as a tube and disposed within the tower and may have axially extending. The media can provide active and/or passive filtration as well as having capabilities to be recharged. Front opening wafer containers for 300 mm sized wafers generally have a pair of recesses on each of the left and right side in the inside rear of the container portions. These recesses are preferably utilized for elongate towers, such towers extending substantially from a bottom wafer position to a top wafer position. In alternative embodiment, a tubular shape of getter material is exposed within the front opening container without containment of the getter other than at the ends. The tubular getter form is preferably supported at discrete locations to maximize exposure to the internal container environment. A blocker member can selectively close the apertures. An elastomeric cap can facilitate securement of the tubular component in the container portion.

摘要翻译： 晶片容器利用具有槽的刚性聚合物管状塔和其中的“吸气剂”，用于吸收和过滤晶片容器内的水分和蒸气。 塔优选在容器的底部使用吹扫索环，并且可以在其中具有止回阀以控制进入和离开容器的气体（包括空气）的流动方向并相对于塔。 塔与护环密封连接。 塔可以具有以细长的圆形方式卷绕的吸气剂介质片，其形成或成形为管，并且设置在塔内并且可以具有轴向延伸。 介质可以提供主动和/或无源过滤以及具有再充电能力。 用于300mm尺寸晶片的前开口晶片容器通常在容器部分的内侧后部的左侧和右侧各具有一对凹部。 这些凹槽优选地用于细长塔，这种塔基本上从底部晶片位置延伸到顶部晶片位置。 在替代实施例中，吸气剂材料的管状形状暴露在前开口容器内，而不会吸收除了末端之外的吸气剂。 管状吸气剂形式优选地在离散位置处被支撑以最大程度地暴露于内部容器环境。 阻挡件可以选择性地封闭孔。 弹性帽可有助于管状部件固定在容器部分中。

公开(公告)号：US07088288B1

公开(公告)日：2006-08-08

申请号：US10340006

申请日：2003-01-10

申请人： Michael A. Margolese ,  James A. Watson

发明人： Michael A. Margolese ,  James A. Watson

IPC分类号： H01Q3/00 ,  H04M1/00

CPC分类号： H01Q3/2605

摘要： A method of controlling an antenna system of a wireless communication network having a plurality of cells is disclosed. The method comprises the steps of determining antenna weights to enable communication between a wireless communication network and the wireless communication device within the wireless communication network; storing the antenna weights in a programmable memory associated with the wireless communication network; and providing predetermined stored antenna weights to the antenna system based upon a location of the wireless communication device. A circuit and wireless communication network for controlling an antenna system are also disclosed.

摘要翻译： 公开了一种控制具有多个小区的无线通信网络的天线系统的方法。 该方法包括以下步骤：确定天线权重以实现无线通信网络内无线通信网络与无线通信设备之间的通信; 将所述天线权重存储在与所述无线通信网络相关联的可编程存储器中; 并且基于所述无线通信设备的位置，向所述天线系统提供预定的存储的天线权重。 还公开了一种用于控制天线系统的电路和无线通信网络。

公开(公告)号：US06897679B2

公开(公告)日：2005-05-24

申请号：US10356691

申请日：2003-01-31

申请人： Richard G. Cliff ,  L. Todd Cope ,  Cameron R. Mc Clintock ,  William Leong ,  James A. Watson ,  Joseph Huang ,  Bahram Ahanin

发明人： Richard G. Cliff ,  L. Todd Cope ,  Cameron R. Mc Clintock ,  William Leong ,  James A. Watson ,  Joseph Huang ,  Bahram Ahanin

IPC分类号： G01R31/3185 ,  G11C8/12 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17736 ,  G01R31/318516 ,  G11C8/12 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728

摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (“LABs”). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

摘要翻译： 可编程逻辑阵列集成电路具有多个可编程逻辑模块，它们被组合在多个逻辑阵列块（“LAB”）中。 LAB以二维阵列布置在电路上。 提供一个导线网络，用于将任何逻辑模块与任何其他逻辑模块相互连接。 此外，相邻或附近的逻辑模块可以彼此连接，用于在逻辑模块之间提供进位链和/或用于将两个或多个模块连接在一起以提供更复杂的逻辑功能而不必利用一般互连的特殊目的 网络。 提供了所谓的快速或通用导体的另一网络，用于在整个电路中分布广泛使用的逻辑信号，例如时钟和清除信号。 多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。

公开(公告)号：US5909375A

公开(公告)日：1999-06-01

申请号：US716908

申请日：1996-09-19

申请人： Cameron McClintock ,  James A. Watson ,  Caleb Crome

发明人： Cameron McClintock ,  James A. Watson ,  Caleb Crome

IPC分类号： G01R31/317 ,  G01R31/3181 ,  G06F17/50

CPC分类号： G01R31/3181 ,  G01R31/31713 ,  G06F17/5022 ,  Y02T10/82

摘要： A system and method for making and using integrated circuits using a modeling system. The system utilizes a pin test buffer. The pin test buffer inputs external inputs to a pin, and outputs to the same pin from the device. If contention is noted between the system inputs to the pin, and outputs from the device to the pin, contention error notices are provided to the user.

摘要翻译： 使用建模系统制造和使用集成电路的系统和方法。 系统使用引脚测试缓冲区。 引脚测试缓冲器将引脚的外部输入输入，并从器件输出到同一引脚。 如果在引脚的系统输入和从器件到引脚的输出之间发生争用，则向用户提供争用错误通知。

公开(公告)号：US07512188B1

公开(公告)日：2009-03-31

申请号：US10412532

申请日：2003-04-10

申请人： James A. Watson ,  Michael A. Margolese

发明人： James A. Watson ,  Michael A. Margolese

IPC分类号： H04L27/18 ,  H04L27/20 ,  H03C5/00 ,  H03D5/00

CPC分类号： H04L27/2003

摘要： The present invention relates to a system for communicating between two integrated circuits (ICs) or within an IC. The ICs are either on the same circuit boards or on different circuit boards with a common backplane. The system comprises a first integrated circuit having an output circuit for generating phase shift keying signals and a second integrated circuit having an input circuit for decoding the phase shift keying signals. The output circuit may include a ring oscillator for generating multiple clock signals that are phase-locked to one another.

摘要翻译： 本发明涉及用于在两个集成电路（IC）之间或内部进行通信的系统。 IC集成在同一个电路板上，或者在具有公共背板的不同电路板上。 该系统包括具有用于产生相移键控信号的输出电路的第一集成电路和具有用于解码相移键控信号的输入电路的第二集成电路。 输出电路可以包括用于产生相互锁相的多个时钟信号的环形振荡器。