公开(公告)号：US5173621A

公开(公告)日：1992-12-22

申请号：US728988

申请日：1991-07-12

申请人： Dana Fraser ,  Ray A. Mentzer ,  Jerry Gray ,  Geoff Hannington ,  Susan M. Keown ,  Gaetan L. Mathieu

发明人： Dana Fraser ,  Ray A. Mentzer ,  Jerry Gray ,  Geoff Hannington ,  Susan M. Keown ,  Gaetan L. Mathieu

IPC分类号： H01L23/495 ,  H01L23/50 ,  H01L23/64 ,  H03K19/003 ,  H03K19/018

CPC分类号： H01L23/50 ,  H01L23/49541 ,  H01L23/645 ,  H03K19/00353 ,  H03K19/01806 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011

摘要： Circuit configurations are described for use with split lead leadframes and relatively isolated quiet and noisy power rails to reduce power rail noise and circuit noise. An octal register transceiver circuit incorporates a latch (300) coupled to relatively quiet power rails (42,44) and an output buffer circuit (400) having an input circuit coupled to the latch (300) and relatively quiet power rails (42,44). The output driver transistors (Q433,Q434) of the output buffer circuit (400) are coupled to the relatively noisy output power rails (52,54) to isolate the latch circuit from power rail noise and minimize erroneous operation of the latch. A DC Miller Killer circuit (450) is constructed with delay control components (D456,D457,R460) and an alternative discharge path (R458,D459) to reduce aggravation of power rail noise during operation of DCMK.

摘要翻译： 电路配置被描述用于分离引线引线框架和相对隔离的安静和噪声电源轨，以减少电力轨道噪声和电路噪声。 八进制寄存器收发器电路包括耦合到相对安静的电源轨（42,44）的锁存器（300）和具有耦合到锁存器（300）和相对安静的电源轨（42,44）的输入电路的输出缓冲器电路（400） ）。 输出缓冲电路（400）的输出驱动晶体管（Q433，Q434）耦合到相对较嘈杂的输出电源轨（52,54），以将锁存电路与电源轨噪声隔离开来并最大限度地减小锁存器的错误操作。 DC Miller Killer电路（450）由延迟控制组件（D456，D457，R460）和替代放电路径（R458，D459）构成，以减少DCMK运行期间电源轨噪声的恶化。

公开(公告)号：US06639569B2

公开(公告)日：2003-10-28

申请号：US09736931

申请日：2000-12-14

申请人： Jerry Gray Kearns ,  Mahendra Somasara Dassanayake ,  Terry Thomas Cwik

发明人： Jerry Gray Kearns ,  Mahendra Somasara Dassanayake ,  Terry Thomas Cwik

IPC分类号： G09G500

CPC分类号： G02B27/0101 ,  B60K2350/2052 ,  G02B2027/0165 ,  G09G3/14 ,  G09G5/02

摘要： An integrated heads-up display (HUD) and cluster projection panel assembly for a motor vehicle includes a housing and a display unit contained within the housing. The display unit has first and second pixel arrays which turn on and off for forming first and second image light beams in response to receiving light. A HUD unit is contained within the housing. The HUD unit has a first converter for transmitting light to the first pixel array of the display unit. The HUD unit further has a first projection optic for projecting the first image light beam from the first pixel array of the display unit onto a windscreen of the motor vehicle. A cluster projection panel unit is contained within the housing. The cluster projection panel has a second converter for transmitting light to the second pixel array of the display unit. The cluster projection panel unit further has a second projection optic for projecting the second image light beam from the second pixel array of the display unit onto a cluster projection screen of the motor vehicle.

公开(公告)号：US5065224A

公开(公告)日：1991-11-12

申请号：US243195

申请日：1988-09-08

申请人： Dana Fraser ,  Ray A. Mentzer ,  Jerry Gray ,  Geoff Hannington ,  Susan M. Keown ,  Gaetan L. Mathieu

发明人： Dana Fraser ,  Ray A. Mentzer ,  Jerry Gray ,  Geoff Hannington ,  Susan M. Keown ,  Gaetan L. Mathieu

IPC分类号： H01L23/495 ,  H01L23/50 ,  H01L23/64 ,  H03K19/003 ,  H03K19/018

CPC分类号： H01L23/645 ,  H01L23/49541 ,  H01L23/50 ,  H03K19/00353 ,  H03K19/01806 ,  H01L2924/0002 ,  H01L2924/30107 ,  H01L2924/3011

摘要： To reduce the effect of on-chip power rail perturbation on integrated circuit performance, a lead configuration is provided having two or more leads originating at a single terminal, e.g. a pin. While merged near the pin in a common segment, the leads connect on the integrated circuit chip to respective isolated internal rails of the same type serving respective device stages. Preferably, the inductance of the common segment is minimized. In accordance with the invention, an octal registered transceiver is provided with isolated V.sub.cc and ground rails for the latch and output buffers. The lead configuration described above is used for both V.sub.cc and ground. Several circuits are improved to optimize performance of the device, including a DC Miller killer circuit. Also in accordance with the invention, the paddle of a PDIP leadframe is supported by tiebars that extends to the dambars at the sides of the leadframe. An additional lead is obtained from a conductive element originating near the paddle and supported by one of the two lead frame rails.

摘要翻译： 为了减少片上电源轨扰动对集成电路性能的影响，提供了一种引线配置，其具有源自单个端子的两个或更多个引线，例如， 一个针。 当引脚在公共部分附近合并时，引线将集成电路芯片连接到相同类型的相互隔离的内部导轨，用于各个器件级。 优选地，公共片段的电感最小化。 根据本发明，八进制寄存收发器具有用于锁存和输出缓冲器的隔离Vcc和接地线。 上述引线结构用于Vcc和地线两者。 改进了几个电路以优化器件的性能，包括DC Miller杀手电路。 同样根据本发明，PDIP引线框的桨由在延伸到引线框架侧面的堤坝的拉杆支撑。 从源于接近桨叶并由两个引线框架轨道中的一个支撑的导电元件获得另外的引线。